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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by: DSP56364/D Rev 3.1 11/00 Advance Information DSP56364 24-Bit Audio Digital Signal Processor The DSP56364 supports digital audio applications requiring sound field processing, acoustic equalization, and other digital audio algorithms. The DSP56364 uses the high performance, single-clock-per-cycle DSP56300 core family of programmable CMOS digital signal processors (DSPs) combined with the audio signal processing capability of the Motorola SymphonyTM DSP family, as shown in Figure 1. This design provides a two-fold performance increase over Motorola's popular Symphony family of DSPs while retaining code compatibility. Significant architectural enhancements include a barrel shifter, 24-bit addressing, instruction cache, and direct memory access (DMA). The DSP56364 offers 100 million instructions per second (MIPS) using an internal 100 MHz clock at 3.3 V. 4 12 5 GPIO ESAI SHI PROGRAM RAM 0.5K x 24 PROGRAM ROM 8K x 24 X MEMORY RAM 1K X 24 Y MEMORY RAM 1.5K X 24 PIO_EB PM_EB XM_EB YM_EB PERIPHERAL EXPANSION AREA ADDRESS GENERATION UNIT SIX CHANNELS DMA UNIT Bootstrap ROM 192 x 24 MEMORY EXPANSION AREA ADDRESS EXTERNAL ADDRESS BUS SWITCH 18 YAB XAB PAB DAB 24-BIT DSP56300 CORE DDB INTERNAL DATA BUS SWITCH YDB XDB PDB GDB DRAM & SRAM BUS INTERFACE CONTROL 6 EXTERNAL DA BUS TA SWITCH DATA 8 POWER MGMT PLL CLOCK PROGRAM INTERRUPT CONT PROGRAM DECODE CONT PROGRAM ADDRESS GEN DATA ALU 24 X 24+5656-BIT MAC TWO 56-BIT ACCUMULATORS BARREL SHIFTER 4 JTAG OnCETM EXTAL RESET PINIT/NMI MODA/IRQA MODB/IRQB MODD/IRQD 24 BITS BUS Figure 1 DSP56364 Block Diagram This document contains information on a new product. Specifications and information herein are subject to change without notice. Advance Information (c)2000 MOTOROLA, INC. DSP56364 PRELIMINARY ii DSP56364 Advance Information MOTOROLA SIGNAL/CONNECTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 IBIS MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 INDEX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INDEX-I FOR TECHNICAL ASSISTANCE: Telephone: Email: Internet: 1-800-521-6274 dsphelp@dsp.sps.mot.com http://www.motorola-dsp.com Data Sheet Conventions This data sheet uses the following conventions: OVERBAR "asserted" "deasserted" Examples: Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) Means that a high true (active high) signal is high or that a low true (active low) signal is low Means that a high true (active high) signal is low or that a low true (active low) signal is high Signal/Symbol PIN PIN PIN PIN Note: Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage* VIL/VOL VIH/VOH VIH/VOH VIL/VOL *Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. !! DSP56362 Advance Information MOTOROLA PRELIMINARY iv DSP56362/D MOTOROLA DSP56364 Features FEATURES Digital Signal Processing Core * * * * * * * * * * 100 Million Instructions Per Second (MIPS) with an 100 MHz clock at 3.3V. Object Code Compatible with the 56000 core. Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic support. Program Control with position independent code support and instruction cache support. Six-channel DMA controller. PLL based clocking with a wide range of frequency multiplications (1 to 4096), predivider factors (1 to 16) and power saving clock divider (2 i: i=0 to 7). Reduces clock noise. Internal address tracing support and OnCETM for Hardware/Software debugging. JTAG port. Very low-power CMOS design, fully static design with operating frequencies down to DC. STOP and WAIT low-power standby modes. On-chip Memory Configuration * * * * * 1.5Kx24 Bit Y-Data RAM. 1Kx24 Bit X-Data RAM. 8Kx24 Bit Program ROM. 0.5Kx24 Bit Program RAM and 192x24 Bit Bootstrap ROM. 0.75Kx24 Bit from Y Data RAM can be switched to Program RAM resulting in up to 1.25Kx24 Bit of Program RAM. Off-chip memory expansion * * External Memory Expansion Port with 8-bit data bus. Off-chip expansion up to 2 x 16M x 8-bit word of Data/Program memory when using DRAM. MOTOROLA DSP56364 Advance Information v DSP56364 Features * * Off-chip expansion up to 2 x 256k x 8-bit word of Data/Program memory when using SRAM. Simultaneous glueless interface to SRAM and DRAM. Peripheral modules * Enhanced Serial Audio Interface (ESAI): 6 serial lines, 4 selectable as receive or transmitt and 2 transmitt only, master or slave. I2S, Sony, AC97, network and other programmable protocols. Unused pins of ESAI may be used as GPIO lines. Serial Host Interface (SHI): SPI and I2C protocols, 10-word receive FIFO, support for 8, 16 and 24-bit words. Four dedicated GPIO lines. * * Packaging * 100-pin plastic TQFP package. vi DSP56364 Advance Information MOTOROLA DSP56364 Documentation DOCUMENTATION Table 1 lists the documents that provide a complete description of the DSP56364 and are required to design properly with the part. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola DSP home page on the Internet (the source for the latest information). Table 1 Document Name DSP56300 Family Manual DSP56364 Documentation Description Order Number DSP56300FM/AD Detailed description of the 56000-family architecture and the 24-bit core processor and instruction set Detailed description of memory, peripherals, and interfaces Electrical and timing specifications; pin and package descriptions DSP56364 User's Manual DSP56364 Technical Data Sheet DSP56364UM/AD DSP56364/D There is also a product brief for this chip. DSP56364 Product Brief Brief description of the chip DSP56364P/D MOTOROLA DSP56364 Advance Information vii DSP56364 Documentation viii DSP56364 Advance Information MOTOROLA SECTION 1 SIGNAL/CONNECTION DESCRIPTIONS SIGNAL GROUPINGS The input and output signals of the DSP56364 are organized into functional groups, which are listed in Table 0-1. and illustrated in Figure 0-1.. The DSP56364 is operated from a 3.3 V supply; however, some of the inputs can tolerate 5 V. A special notice for this feature is added to the signal descriptions of those inputs. Table 1-1. DSP56364 Functional Signal Groupings Functional Group Power (VCC) Ground (GND) Clock and PLL Address bus Data bus Bus control Interrupt and mode control General Purpose I/O SHI ESAI JTAG/OnCE Port Notes: 1. 2. 3. Port C3 Port B2 Number of Signals 18 14 3 18 Port A1 8 6 4 4 5 12 4 Detailed Description Table 0-2. Table 0-3. Table 0-4. Table 0-5. Table 0-6. Table 0-7. Table 0-8. Table 0-12 Table 0-9. Table 0-10. Table 0-11. Port A is the external memory interface port, including the external address bus, data bus, and control signals. Port B signals are the GPIO signals. Port C signals are the ESAI port signals multiplexed with the GPIO signals. MOTOROLA DSP56364 Advance Information 1-1 Signal/Connection Descriptions Signal Groupings PORT A ADDRESS BUS A0-A17 VCCA (4) GNDA (4) OnCETM ON-CHIP EMULATION/ JTAG PORT DSP56364 Port B GPIO TDI TCK TDO TMS PORT A DATA BUS D0-D7 VCCD (1) GNDD (1) PB0-PB3 PORT A BUS CONTROL AA0-AA1/RAS0-RAS1 CAS RD WR TA VCCC (1) GNDC (1) RESERVED (4) SERIAL AUDIO INTERFACE (ESAI) Port C SCKT [PC3] FST [PC4] HCKT [PC5] SCKR [PC0] FSR [PC1] HCKR [PC2] SDO0 [PC11] SDO1 [PC10] SDO2/SDI3 [PC9] SDO3/SDI2 [PC8] SDO4/SDI1 [PC7] SDO5/SDI0 [PC6] VCCSS (3) GNDS (3) INTERRUPT AND MODE CONTROL MODA/IRQA MODB/IRQB MODD/IRQD RESET PLL AND CLOCK PINIT/NMI PCAP VCCP GNDP EXTAL SERIAL HOST INTERFACE (SHI) MOSI/HA0 SS/HA2 MISO/SDA SCK/SCL HREQ QUIET POWER VCCHQ (4) VCCLQ (4) GNDQ (4) Figure 1-1. Signals Identified by Functional Group 1-2 DSP56364 Advance Information MOTOROLA Signal/Connection Descriptions Power POWER Table 1-2. Power Inputs Power Name Description PLL Power--VCCP is VCC dedicated for PLL use. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. There is one VCCP input. Quiet Core (Low) Power--VCCQL is an isolated power for the internal processing logic. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are four VCCQL inputs. Quiet External (High) Power--VCCQH is a quiet power source for I/O lines. This input must be tied externally to all other chip power inputs. The user must provide adequate decoupling capacitors. There are four VCCQH inputs. Address Bus Power--VCCA is an isolated power for sections of the address bus I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are four VCCA inputs. Data Bus Power--VCCD is an isolated power for sections of the data bus I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There is one VCCD inputs. Bus Control Power--VCCC is an isolated power for the bus control I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There is one VCCC inputs. SHI and ESAI --VCCS is an isolated power for the SHI and ESAI. This input must be tied externally to all other chip power inputsL. The user must provide adequate external decoupling capacitors. There are three VCCS inputs. VCCP VCCQL (4) VCCQH (4) VCCA (4) VCCD (1) VCCC (1) VCCS (3) MOTOROLA DSP56364 Advance Information 1-3 Signal/Connection Descriptions Ground GROUND Table 1-3. Grounds Ground Name Description PLL Ground--GNDP is ground-dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. VCCP should be bypassed to GNDP by a 0.47 F capacitor located as close as possible to the chip package. There is one GNDP connection. Quiet Ground--GNDQ is an isolated ground for the internal processing logic. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GNDQ connections. Address Bus Ground--GNDA is an isolated ground for sections of the address bus I/ O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GNDA connections. Data Bus Ground--GNDD is an isolated ground for sections of the data bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There is one GNDD connections. Bus Control Ground--GNDC is an isolated ground for the bus control I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There is one GND C connections. SHI and ESAI --GNDS is an isolated ground for the SHI and ESAI. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are three GNDS connections. GNDP GNDQ (4) GNDA (4) GNDD (1) GNDC (1) GNDS (3) 1-4 DSP56364 Advance Information MOTOROLA Signal/Connection Descriptions Clock and PLL CLOCK AND PLL Table 1-4. Clock and PLL Signals Signal Name Type State during Reset Signal Description EXTAL Input Input External Clock Input--An external clock source must be connected to EXTAL in order to supply the clock to the internal clock generator and PLL. PLL Capacitor--PCAP is an input connecting an off-chip capacitor to the PLL filter. Connect one capacitor terminal to PCAP and the other terminal to VCCP. If the PLL is not used, PCAP may be tied to VCC, GND, or left floating. PLL Initial/Nonmaskable Interrupt--During assertion of RESET, the value of PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register, determining whether the PLL is enabled or disabled. After RESET de assertion and during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a negative-edge-triggered nonmaskable interrupt (NMI) request internally synchronized to internal system clock. This input is 5 V tolerant. PCAP Input Input PINIT/ NMI Input Input MOTOROLA DSP56364 Advance Information 1-5 Signal/Connection Descriptions External Memory Expansion Port (Port A) EXTERNAL MEMORY EXPANSION PORT (PORT A) When the DSP56364 enters a low-power standby mode (stop or wait), it tri-states the relevant port A signals: D0-D7, AA0, AA1, RD, WR, CAS. External Address Bus Table 1-5. External Address Bus Signals Signal Name Type State during Reset Signal Description A0-A17 Outp ut Keeper active Address Bus--A0-A17 are active-high outputs that specify the address for external program and data memory accesses. Otherwise, the signals are kept to their previous values by internal weak keepers. To minimize power dissipation, A0-A17 do not change state when external memory spaces are not being accessed. External Data Bus Table 1-6. External Data Bus Signals Signal Name Type State during Reset Signal Description Data Bus--D0-D7 are active-high, bidirectional input/ outputs that provide the bidirectional data bus for external program and data memory accesses. D0-D7 are tri-stated during hardware reset and when the DSP is in the stop or wait low-power standby mode. D0-D7 Input/ Output Tri-stated 1-6 DSP56364 Advance Information MOTOROLA Signal/Connection Descriptions External Memory Expansion Port (Port A) External Bus Control Table 1-7. External Bus Control Signals Signal Name Type State during Reset Signal Description AA0- AA1/ RAS0- RAS1 Outp ut Tristated Address Attribute or Row Address Strobe--When defined as AA, these signals can be used as chip selects or additional address lines. When defined as RAS, these signals can be used as RAS for DRAM interface. These signals are tri-statable outputs with programmable polarity. These signals are tri-stated during hardware reset and when the DSP is in the stop or wait low-power standby mode. Column Address Strobe-- CAS is an active-low output used by DRAM to strobe the column address. This signal is tri-stated during hardware reset and when the DSP is in the stop or wait low-power standby mode. Read Enable--RD is an active-low output that is asserted to read external memory on the data bus. This signal is tri-stated during hardware reset and when the DSP is in the stop or wait low-power standby mode. Write Enable-- WR is an active-low output that is asserted to write external memory on the data bus. This signal is tri-stated during hardware reset and when the DSP is in the stop or wait low-power standby mode. Transfer Acknowledge--If there is no external bus activity, the TA input is ignored. The TA input is a data transfer acknowledge (DTACK) function that can extend an external bus cycle indefinitely. Any number of wait states (1, 2. . .infinity) may be added to the wait states inserted by the BCR by keeping TA deasserted. In typical operation, TA is deasserted at the start of a bus cycle, is asserted to enable completion of the bus cycle, and is deasserted before the next bus cycle. The current bus cycle completes one clock period after TA is asserted synchronous to the internal system clock. The number of wait states is determined by the TA input or by the bus control register (BCR), whichever is longer. The BCR can be used to set the minimum number of wait states in external bus cycles. In order to use the TA functionality, the BCR must be programmed to at least one wait state. A zero wait state access cannot be extended by TA deassertion, otherwise improper operation may result. TA can operate synchronously or asynchronously, depending on the setting of the TAS bit in the operating mode register (OMR). TA functionality may not be used while performing DRAM type accesses, otherwise improper operation may result. CAS Outp ut Tristated RD Outp ut Tristated WR Outp ut Tristated TA Input Ignored Input MOTOROLA DSP56364 Advance Information 1-7 Signal/Connection Descriptions Interrupt and Mode Control INTERRUPT AND MODE CONTROL The interrupt and mode control signals select the chip's operating mode as it comes out of hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines. Table 1-8. Interrupt and Mode Control Stat e duri ng Rese t Signal Name Type Signal Description MODA/IRQA Input Input Mode Select A/External Interrupt Request A--MODA/IRQA is an active-low Schmitt-trigger input, internally synchronized to the internal system clock. MODA/IRQA selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negativeedge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, and MODD select one of 8 initial chip operating modes, latched into the OMR when the RESET signal is deasserted. If IRQA is asserted synchronous to the internal system clock, multiple processors can be re synchronized using the WAIT instruction and asserting IRQA to exit the wait state. If the processor is in the stop standby state and IRQA is asserted, the processor will exit the stop state. This input is 5 V tolerant. Mode Select B/External Interrupt Request B--MODB/IRQB is an active-low Schmitt-trigger input, internally synchronized to the internal system clock. MODB/IRQB selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negativeedge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, and MODD select one of 8 initial chip operating modes, latched into OMR when the RESET signal is deasserted. If IRQB is asserted synchronous to the internal system clock, multiple processors can be re-synchronized using the WAIT instruction and asserting IRQB to exit the wait state. This input is 5 V tolerant. MODB/IRQB Input Input 1-8 DSP56364 Advance Information MOTOROLA Signal/Connection Descriptions Interrupt and Mode Control Table 1-8. Interrupt and Mode Control (Continued) Stat e duri ng Rese t Signal Name Type Signal Description MODD/IRQD Input Input Mode Select D/External Interrupt Request D--MODD/IRQD is an active-low Schmitt-trigger input, internally synchronized to the internal system clock. MODD/IRQD selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negativeedge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, and MODD select one of 8 initial chip operating modes, latched into OMR when the RESET signal is deasserted. If IRQD is asserted synchronous to the internal system clock, multiple processors can be re synchronized using the WAIT instruction and asserting IRQD to exit the wait state. This input is 5 V tolerant. Reset--RESET is an active-low, Schmitt-trigger input. When asserted, the chip is placed in the reset state and the internal phase generator is reset. The Schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. When the RESET signal is deasserted, the initial chip operating mode is latched from the MODA, MODB, and MODD inputs. The RESET signal must be asserted during power up. A stable EXTAL signal must be supplied before deassertionof RESET. This input is 5 V tolerant. RESET Input Input MOTOROLA DSP56364 Advance Information 1-9 Signal/Connection Descriptions Serial Host Interface SERIAL HOST INTERFACE The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I2C mode. Table 1-9. Serial Host Interface Signals Signal Name Signal Type State during Reset Signal Description SCK Input or output Tristated Input or output SPI Serial Clock--The SCK signal is an output when the SPI is configured as a master and a Schmitt-trigger input when the SPI is configured as a slave. When the SPI is configured as a master, the SCK signal is derived from the internal SHI clock generator. When the SPI is configured as a slave, the SCK signal is an input, and the clock signal from the external master synchronizes the data transfer. The SCK signal is ignored by the SPI if it is defined as a slave and the slave select (SS) signal is not asserted. In both the master and slave SPI devices, data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable. Edge polarity is determined by the SPI transfer protocol. I2C Serial Clock--SCL carries the clock for I2C bus transactions in the I2C mode. SCL is a Schmitt-trigger input when configured as a slave and an open-drain output when configured as a master. SCL should be connected to VCC through a pull-up resistor. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 5 V tolerant. SCL 1-10 DSP56364 Advance Information MOTOROLA Signal/Connection Descriptions Serial Host Interface Table 1-9. Serial Host Interface Signals (Continued) Signal Name Signal Type State during Reset Signal Description MISO Input or output SPI Master-In-Slave-Out--When the SPI is configured as a master, MISO is the master data input line. The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data. This signal is a Schmitt-trigger input when configured for the SPI Master mode, an output when configured for the SPI Slave mode, and tri-stated if configured for the SPI Slave mode when SS is deasserted. An external pull-up resistor is not required for SPI operation. I2C Data and Acknowledge--In I2C mode, SDA is a Schmitt-trigger input when receiving and an open-drain output when transmitting. SDA should be connected to VCC through a pull-up resistor. SDA carries the data for I2C transactions. The data in SDA must be stable during the high period of SCL. The data in SDA is only allowed to change when SCL is low. When the bus is free, SDA is high. The SDA line is only allowed to change during the time SCL is high in the case of start and stop events. A high-to-low transition of the SDA line while SCL is high is a unique situation, and is defined as the start event. A low-to-high transition of SDA while SCL is high is a unique situation defined as the stop event. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 5 V tolerant. SPI Master-Out-Slave-In--When the SPI is configured as a master, MOSI is the master data output line. The MOSI signal is used in conjunction with the MISO signal for transmitting and receiving serial data. MOSI is the slave data input line when the SPI is configured as a slave. This signal is a Schmitt-trigger input when configured for the SPI Slave mode. Tristated I2C Slave Address 0--This signal uses a Schmitt-trigger input when configured for the I2C mode. When configured for I2C slave mode, the HA0 signal is used to form the slave device address. HA0 is ignored when configured for the I2C master mode. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 5 V tolerant. SDA Input or opendrain output Tristated MOSI Input or output HA0 Input MOTOROLA DSP56364 Advance Information 1-11 Signal/Connection Descriptions Serial Host Interface Table 1-9. Serial Host Interface Signals (Continued) Signal Name Signal Type State during Reset Signal Description SS Input Input HA2 SPI Slave Select--This signal is an active low Schmitt-trigger input when configured for the SPI mode. When configured for the SPI Slave mode, this signal is used to enable the SPI slave for transfer. When configured for the SPI master mode, this signal should be kept deasserted (pulled high). If it is asserted while configured as SPI master, a bus error condition is flagged. If SS is deasserted, the SHI ignores SCK clocks and keeps the MISO output signal in the highimpedance state. I2C Slave Address 2--This signal uses a Schmitt-trigger input when configured for the I2C mode. When configured for the I2C Slave mode, the HA2 signal is used to form the slave device address. HA2 is ignored in the I2C master mode. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 5 V tolerant. Input or Output Host Request--This signal is an active low Schmitt-trigger input when configured for the master mode but an active low output when configured for the slave mode. When configured for the slave mode, HREQ is asserted to indicate that the SHI is ready for the next data word transfer and deasserted at the first clock pulse of the new data word transfer. When configured for the master mode, HREQ is an input. When asserted by the external slave device, it will trigger the start of the data word transfer by the master. After finishing the data word transfer, the master will await the next assertion of HREQ to proceed to the next transfer. This signal is tri-stated during hardware, software, personal reset, or when the HREQ1-HREQ0 bits in the HCSR are cleared. There is no need for external pull-up in this state. HREQ Tristated This input is 5 V tolerant. 1-12 DSP56364 Advance Information MOTOROLA Signal/Connection Descriptions Enhanced Serial Audio Interface ENHANCED SERIAL AUDIO INTERFACE Table 1-10. Enhanced Serial Audio Interface Signals Signal Name Signal Type State during Reset Signal Description High Frequency Clock for Receiver--When programmed as an input, this signal provides a high frequency clock source for the ESAI receiver as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high-frequency sample clock (e.g., for external digital to analog converters [DACs]) or as an additional system clock. GPIO disconnected Port C 2--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. HCKR Input or output PC2 Input, output, or disconnected This input is 5 V tolerant. High Frequency Clock for Transmitter--When programmed as an input, this signal provides a high frequency clock source for the ESAI transmitter as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high frequency sample clock (e.g., for external DACs) or as an additional system clock. Port C 5--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. HCKT Input or output PC5 Input, output, or disconnected GPIO disconnected MOTOROLA DSP56364 Advance Information 1-13 Signal/Connection Descriptions Enhanced Serial Audio Interface Table 1-10. Enhanced Serial Audio Interface Signals (Continued) Signal Name Signal Type State during Reset Signal Description Frame Sync for Receiver--This is the receiver frame sync input/output signal. In the asynchronous mode (SYN=0), the FSR pin operates as the frame sync input or output used by all the enabled receivers. In the synchronous mode (SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable control (TEBE=1, RFSD=1). FSR Input or output When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in the RCCR register. When configured as the output flag OF1, this pin will reflect the value of the OF1 bit in the SAICR register, and the data in the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF1, the data value at the pin will be stored in the IF1 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. Port C 1--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. Frame Sync for Transmitter--This is the transmitter frame sync input/output signal. For synchronous mode, this signal is the frame sync for both transmitters and receivers. For asynchronous mode, FST is the frame sync for the transmitters only. The direction is determined by the transmitter frame sync direction (TFSD) bit in the ESAI transmit clock control register (TCCR). GPIO disconnected PC4 Input, output, or disconnected Port C 4--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. GPIO disconnected PC1 Input, output, or disconnected FST Input or output 1-14 DSP56364 Advance Information MOTOROLA Signal/Connection Descriptions Enhanced Serial Audio Interface Table 1-10. Enhanced Serial Audio Interface Signals (Continued) Signal Name Signal Type State during Reset Signal Description Receiver Serial Clock--SCKR provides the receiver serial bit clock for the ESAI. The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1). When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR register. When configured as the output flag OF0, this pin will reflect the value of the OF0 bit in the SAICR register, and the data in the OF0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF0, the data value at the pin will be stored in the IF0 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. Port C 0--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. Transmitter Serial Clock--This signal provides the serial bit rate clock for the ESAI. SCKT is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode. GPIO disconnected Port C 3--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. SCKR Input or output GPIO disconnected PC0 Input, output, or disconnected SCKT Input or output PC3 Input, output, or disconnected MOTOROLA DSP56364 Advance Information 1-15 Signal/Connection Descriptions Enhanced Serial Audio Interface Table 1-10. Enhanced Serial Audio Interface Signals (Continued) Signal Name Signal Type State during Reset Signal Description Serial Data Output 5--When programmed as a transmitter, SDO5 is used to transmit data from the TX5 serial transmit shift register. Serial Data Input 0--When programmed as a receiver, SDI0 is used to receive serial data into the RX0 serial receive shift register. Port C 6--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. Serial Data Output 4--When programmed as a transmitter, SDO4 is used to transmit data from the TX4 serial transmit shift register. Serial Data Input 1--When programmed as a receiver, SDI1 is used to receive serial data into the RX1 serial receive shift register. Port C 7--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. SDO5 Output SDI0 Input GPIO disconnected PC6 Input, output, or disconnected SDO4 Output SDI1 Input GPIO disconnected PC7 Input, output, or disconnected 1-16 DSP56364 Advance Information MOTOROLA Signal/Connection Descriptions Enhanced Serial Audio Interface Table 1-10. Enhanced Serial Audio Interface Signals (Continued) Signal Name Signal Type State during Reset Signal Description Serial Data Output 3--When programmed as a transmitter, SDO3 is used to transmit data from the TX3 serial transmit shift register. Serial Data Input 2--When programmed as a receiver, SDI2 is used to receive serial data into the RX2 serial receive shift register. Port C 8--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. Serial Data Output 2--When programmed as a transmitter, SDO2 is used to transmit data from the TX2 serial transmit shift register Serial Data Input 3--When programmed as a receiver, SDI3 is used to receive serial data into the RX3 serial receive shift register. Port C 9--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. SDO1 Output Input, output, or disconnected Serial Data Output 1--SDO1 is used to transmit data from the TX1 serial transmit shift register. Port C 10--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. SDO3 Output SDI2 Input GPIO disconnected PC8 Input, output, or disconnected SDO2 Output SDI3 Input GPIO disconnected PC9 Input, output, or disconnected PC10 GPIO disconnected MOTOROLA DSP56364 Advance Information 1-17 Signal/Connection Descriptions JTAG/OnCE Interface Table 1-10. Enhanced Serial Audio Interface Signals (Continued) Signal Name SDO0 Signal Type State during Reset Signal Description Serial Data Output 0--SDO0 is used to transmit data from the TX0 serial transmit shift register. Port C 11--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. Output Input, output, or disconnected PC11 GPIO disconnected JTAG/OnCE INTERFACE Table 1-11. JTAG/OnCE Interface Signal Name Signal Type State during Reset Signal Description TCK Input Input Test Clock--TCK is a test clock input signal used to synchronize the JTAG test logic. It has an internal pull-up resistor. This input is 5 V tolerant. Test Data Input--TDI is a test data serial input signal used for test instructions and data. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor. This input is 5 V tolerant. Test Data Output--TDO is a test data serial output signal used for test instructions and data. TDO is tri-statable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCK. Test Mode Select--TMS is an input signal used to sequence the test controller's state machine. TMS is sampled on the rising edge of TCK and has an internal pull-up resistor. This input is 5 V tolerant. TDI Input Input TDO Output Tristated TMS Input Input 1-18 DSP56364 Advance Information MOTOROLA Signal/Connection Descriptions JTAG/OnCE Interface Table 1-12. GPIO Signals Signal Name Signal Type State during Reset Signal Description GPIO0GPIO3 Input, output or disconnecte d disconn ected GPIO0-3- The General Purpose I/O pins are used for control and handshake functions between the DSP and external circuitry. Each Port B GPIO pin may be individually programmed as an input, output or disconnected MOTOROLA DSP56364 Advance Information 1-19 Signal/Connection Descriptions JTAG/OnCE Interface 1-20 DSP56364 Advance Information MOTOROLA SECTION 2 SPECIFICATIONS INTRODUCTION The DSP56364 is a high density CMOS device with Transistor-Transistor Logic (TTL) compatible inputs and outputs. The DSP56364 specifications are preliminary and are from design simulations, and may not be fully tested or guaranteed. Finalized specifications will be published after full characterization and device qualifications are complete. MAXIMUM RATINGS CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability of operation is enhanced if unused inputs are pulled to an appropriate logic voltage level (e.g., either GND or VCC). The suggested value for a pullup or pulldown resistor is 10 k. Note: In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a "maximum" value for a specification will never occur in the same device that has a "minimum" value for another specification; adding a maximum to a minimum represents a condition that can never exist. MOTOROLA DSP56364 Advance Information 2-1 Specifications Thermal Characteristics Table 2-1. Maximum Ratings Rating1 Supply Voltage All input voltages excluding "5 V tolerant" inputs3 All "5 V tolerant" input voltages3 Current drain per pin excluding VCC and GND Operating temperature range Storage temperature Notes: 1. 2. Symbol VCC VIN VIN5 I TJ TSTG Value1, 2 Unit V V V mA -0.3 to +4.0 GND -0.3 to VCC + 0.3 GND - 0.3 to VCC + 3.95 10 -40 to +105 C C -55 to +125 3. GND = 0 V, VCC = 3.3 V 0.16 V, TJ = -0C to +105C, CL = 50 pF Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. CAUTION: All "5 V Tolerant" input voltages must not be more than 3.95 V greater than the supply voltage; this restriction applies to "power on", as well as during normal operation. In any case, the input voltages cannot be more than 5.75 V. "5 V Tolerant" inputs are inputs that tolerate 5 V. THERMAL CHARACTERISTICS Table 2-2. Thermal Characteristics Characteristic Junction-to-ambient thermal resistance1 Junction-to-case thermal resistance2 Thermal characterization parameter Notes: 1. Symbol RJA or JA RJC or JC JT TQFP Value 49.87 9.26 2.0 Unit C/W C/W C/W 2. Junction-to-ambient thermal resistance is based on measurements on a horizontal single-sided printed circuit board per SEMI G38-87 in natural convection.(SEMI is Semiconductor Equipment and Materials International, 805 East Middlefield Rd., Mountain View, CA 94043, (415) 964-5111.) Measurements were done with parts mounted on thermal test boards conforming to specification EIA/ JESD51-3. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88, with the exception that the cold plate temperature is used for the case temperature. 2-2 DSP56364 Advance Information MOTOROLA Specifications DC Electrical Characteristics DC ELECTRICAL CHARACTERISTICS Table 2-3. DC Electrical Characteristics6 Characteristics Supply voltage Input high voltage * D(0:7), TA * MOD1/IRQ1, RESET, PINIT/NMI and all JTAG/ESAI/GPIO/SHI (SPI mode)pins * SHI (I2C mode) pins * EXTAL8 Input low voltage * D(0:7), TA, MOD1/IRQ1, RESET, PINIT * JTAG/ESAI/GPIO/SHI (SPI mode)pins * SHI (I2C mode) pins * EXTAL8 Input leakage current High impedance (off-state) input current (@ 2.4 V / 0.4 V) Output high voltage * TTL (IOH = -0.4 mA)5,7 * CMOS (IOH = -10 A)5 Output low voltage * TTL (IOL = 3.0 mA, open-drain pins IOL = 6.7 mA)5,7 * CMOS (IOL = 10 A)5 Internal supply current2 at internal clock of 100Mhz * In Normal mode * In Wait mode3 * In Stop mode4 Symbol VCC VIH VIHP VIHP VIHX VIL Min 3.14 2.0 2.0 1.5 0.8 x VCC Typ 3.3 -- -- -- -- Max 3.46 VCC VCC + 3.95 VCC + 3.95 VCC Unit V V -0.3 -0.3 -0.3 -0.3 -10 -10 -- -- -- -- -- -- 0.8 0.8 0.3xVCC 0.2 x VCC 10 10 A A V VILP VILP VILX IIN ITSI VOH 2.4 VCC - 0.01 -- -- -- -- V V VOL -- -- -- -- 0.4 0.01 V ICCI ICCW ICCS -- -- -- 127 7. 5 100 181 11 150 mA mA A MOTOROLA DSP56364 Advance Information 2-3 Specifications DC Electrical Characteristics Table 2-3. DC Electrical Characteristics6 (Continued) Characteristics PLL supply current Input capacitance5 Notes: 1. 2. Symbol Min -- Typ 1 -- Max 2.5 10 Unit mA pF CIN -- 3. 4. 5. 6. 7. 8. Refers to MODA/IRQA, MODB/IRQB, and MODD/IRQD pins Power Consumption Considerations on page 4-4 provides a formula to compute the estimated current requirements in Normal mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are based on synthetic intensive DSP benchmarks. The power consumption numbers in this specification are 90% of the measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with VCC = 3.3 V at TJ = 105C. Maximum internal supply current is measured with VCC = 3.46 V at TJ = 105C. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). PLL signal is disabled during Stop state. In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed to float). Periodically sampled and not 100% tested VCC = 3.3 V .16 V; TJ = 0C to +105C, CL = 50 pF This characteristic does not apply to PCAP. Driving EXTAL to the low VIHX or the high VILX value may cause additional power consumption (DC current). To minimize power consumption, the minimum VIHX should be no lower than 0.9 x VCC and the maximum VILX should be no higher than 0.1 x VCC. 2-4 DSP56364 Advance Information MOTOROLA Specifications AC Electrical Characteristics AC ELECTRICAL CHARACTERISTICS The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of 0.3 V and a VIH minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels shown in Note 8 of the previous table. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50% point of the respective input signal's transition. DSP56364 output levels are measured with the production test machine VOL and VOH reference levels set at 0.4 V and 2.4 V, respectively. Note: Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test conditions are 15 MHz and rated speed. MOTOROLA DSP56364 Advance Information 2-5 Specifications Internal Clocks INTERNAL CLOCKS Table 2-4. Internal Clocks Expression1, 2 Characteristics Symbol Min Internal operation frequency with PLL enabled Internal operation frequency with PLL disabled Internal clock high period * With PLL disabled * With PLL enabled and MF 4 * With PLL enabled and MF > 4 Internal clock low period * With PLL disabled * With PLL enabled and MF 4 * With PLL enabled and MF > 4 Internal clock cycle time with PLL enabled Internal clock cycle time with PLL disabled Instruction cycle time Notes: 1. TC TC ICYC -- 0.49 x ETC x PDF x DF/MF 0.47 x ETC x PDF x DF/MF -- ETC -- -- ETC x PDF x DF/MF 2 x ETC TC -- 0.51 x ETC x PDF x DF/MF 0.53 x ETC x PDF x DF/MF -- TH -- 0.49 x ETC x PDF x DF/MF 0.47 x ETC x PDF x DF/MF ETC -- -- 0.51 x ETC x PDF x DF/MF 0.53 x ETC x PDF x DF/MF f -- Typ (Ef x MF)/ (PDF x DF) Ef/2 Max -- f -- -- -- TL -- -- -- -- 2. DF = Division Factor Ef = External frequency ETC = External clock cycle MF = Multiplication Factor PDF = Predivision Factor TC = internal clock cycle See the PLL and Clock Generation section in the DSP56300 detailed discussion of the PLL. Family Manual for a 2-6 DSP56364 Advance Information MOTOROLA Specifications EXTERNAL CLOCK OPERATION EXTERNAL CLOCK OPERATION The DSP56364 system clock is an externally supplied square wave voltage source connected to EXTAL(Figure 2-1.). VIHC EXTAL VILC ETH 2 4 ETL 3 ETC Midpoint Note: The midpoint is 0.5 (VIHC + VILC). Figure 2-1. External Clock Timing Table 2-5. Clock Operation No. 1 Characteristics Frequency of EXTAL (EXTAL Pin Frequency) The rise and fall time of this external clock should be 3 ns maximum. EXTAL input high1, 2 * With PLL disabled (46.7%-53.3% duty cycle6) * With PLL enabled (42.5%-57.5% duty cycle6) EXTAL input low1, 2 * With PLL disabled (46.7%-53.3% duty cycle6) * With PLL enabled (42.5%-57.5% duty cycle6) 4 EXTAL cycle time2 * With PLL disabled * With PLL enabled Notes: 1. 2. Symbol Ef Min 0 Max 100.0 2 ETH 4.67 ns 4.25 ns 157.0 s 3 ETL 4.67 ns 4.25 ns 157.0 s 273.1 s ETC 10.00 ns 10.00 ns Measured at 50% of the input transition The maximum value for PLL enabled is given for minimum VCO and maximum MF. MOTOROLA DSP56364 Advance Information 2-7 Specifications Phase Lock Loop (PLL) Characteristics PHASE LOCK LOOP (PLL) CHARACTERISTICS Table 2-6. PLL Characteristics Characteristics VCO frequency when PLL enabled (MF x Ef x 2/PDF) PLL external capacitor (PCAP pin to VCCP) (CPCAP1) * @ MF 4 * @ MF > 4 Notes: 1. Min 30 Max 200 Unit MHz (MF x 580) - 100 MF x 830 (MF x 780) - 140 MF x 1470 pF CPCAP is the value of the PLL capacitor (connected between the PCAP pin and VCCP). The recommended value in pF for CPCAP can be computed from one of the following equations: (MF x 680)-120, for MF 4, or MF x 1100, for MF > 4. 2-8 DSP56364 Advance Information MOTOROLA Specifications Reset, Stop, Mode Select, and Interrupt Timing RESET, STOP, MODE SELECT, AND INTERRUPT TIMING Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing6 No. 8 Characteristics Delay from RESET assertion to all pins at reset value3 Required RESET duration4 * Power on, external clock generator, PLL disabled * Power on, external clock generator, PLL enabled 9 * Power on, internal oscillator * During STOP, XTAL disabled (PCTL Bit 16 = 0) * During STOP, XTAL enabled (PCTL Bit 16 = 1) * During normal operation Delay from asynchronous RESET deassertion to first external address output (internal reset 10 deassertion)5 * Minimum * Maximum 13 Mode select setup time 14 Mode select hold time 15 16 Minimum edge-triggered interrupt request assertion width Minimum edge-triggered interrupt request deassertion width Expression -- Min -- Max 26.0 Unit ns 50 x ETC 1000 x ETC 75000 x ETC 75000 x ETC 2.5 x TC 2.5 x TC 500.0 10.0 0.75 0.75 25.0 25.0 -- -- -- -- -- -- ns ns s ms ms ns 3.25 x TC + 2.0 20.25 TC + 7.50 34.5 -- 30.0 0.0 6.6 6.6 -- 211.5 -- -- -- -- ns ns ns ns ns ns Delay from IRQA, IRQB, IRQD, NMI assertion to external memory access address out valid * Caused by first interrupt instruction fetch 17 * Caused by first interrupt instruction execution Delay from IRQA, IRQB, IRQD, NMI assertion 18 to general-purpose transfer output valid caused by first interrupt instruction execution 4.25 x TC + 2.0 7.25 x TC + 2.0 10 x TC + 5.0 44.5 74.5 -- -- ns ns 105.0 -- ns MOTOROLA DSP56364 Advance Information 2-9 Specifications Reset, Stop, Mode Select, and Interrupt Timing Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing6 (Continued) No. Characteristics Expression Min -- Max -- Unit ns Delay from address output valid caused by first 19 interrupt instruction execute to interrupt request 3.75 x TC + WS x TC - 10.94 deassertion for level sensitive fast interrupts1 20 Delay from RD assertion to interrupt request deassertion for level sensitive fast interrupts1 Delay from WR assertion to interrupt request deassertion for level sensitive fast interrupts1 * DRAM for all WS 21 * SRAM WS = 1 * SRAM WS = 2, 3 * SRAM WS 4 24 Duration for IRQA assertion to recover from Stop state Delay from IRQA assertion to fetch of first instruction (when exiting Stop)2, 3 * PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is enabled (OMR Bit 6 = 0) 25 * PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not enabled (OMR Bit 6 = 1) (WS + 3.5) x TC - 10.94 (WS + 3.5) x TC - 10.94 (WS + 3) x TC - 10.94 (WS + 2.5) x TC - 10.94 3.25 x TC + WS x TC - 10.94 -- -- ns -- -- -- -- 5.9 -- ns -- -- -- -- PLC x ETC x PDF + (128 K - PLC/2) x TC 1.3 13.6 ms PLC x ETC x PDF + (23.75 232.5 0.5) x TC ns 77.5 12.3 ms 87.5 ns * PLL is active during Stop (PCTL Bit 17 = (8.25 0.5) x TC 1) (Implies No Stop Delay) Duration of level sensitive IRQA assertion to ensure interrupt service (when exiting Stop)2, 3 * PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is enabled (OMR Bit 6 = 0) 26 * PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not enabled (OMR Bit 6 = 1) * PLL is active during Stop (PCTL Bit 17 = 1) (implies no Stop delay) PLC x ETC x PDF + (128K - PLC/2) x TC PLC x ETC x PDF + (20.5 0.5) x TC 5.5 x TC 13.6 -- ms 12.3 -- ms 55.0 -- ns 2-10 DSP56364 Advance Information MOTOROLA Specifications Reset, Stop, Mode Select, and Interrupt Timing Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing6 (Continued) No. Characteristics Interrupt Requests Rate * ESAI, SCI 27 * DMA * IRQ, NMI (edge trigger) * IRQ, NMI (level trigger) DMA Requests Rate * Data read from ESAI, SCI 28 * Data write to ESAI, SCI * IRQ, NMI (edge trigger) Expression 12TC 8TC 8TC 12TC 6TC 7TC 3TC Min -- -- -- -- -- -- -- Max 120.0 80.0 80.0 120.0 60.0 70.0 30.0 Unit ns ns ns ns ns ns ns MOTOROLA DSP56364 Advance Information 2-11 Specifications Reset, Stop, Mode Select, and Interrupt Timing Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing6 (Continued) No. Characteristics Expression 4.25 x TC + 2.0 Min 44.0 Max -- Unit ns Delay from IRQA, IRQB, IRQD, NMI assertion 29 to external memory (DMA source) access address out valid Notes: 1. When using fast interrupts and IRQA, IRQB, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode. This timing depends on several settings: For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and oscillator disabled during Stop (PCTL Bit 17 = 0), a stabilization delay is required to assure the oscillator is stable before executing programs. In that case, resetting the Stop delay (OMR Bit 6 = 0) will provide the proper delay. While it is possible to set OMR Bit 6 = 1, it is not recommended and these specifications do not guarantee timings for that case. For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit 17=1), no stabilization delay is required and recovery time will be minimal (OMR Bit 6 setting is ignored). For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time will be defined by the PCTL Bit 17 and OMR Bit 6 settings. For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in parallel with the stop delay counter, and stop recovery will end when the last of these two events occurs. The stop delay counter completes count or PLL lock procedure completion. PLC value for PLL disable is 0. The maximum value for ETC is 4096 (maximum MF) divided by the desired internal frequency (i.e., for 100 MHz it is 4096/100 MHz = 40 s). During the stabilization period, TC, TH, and TL will not be constant, and their width may vary, so timing may vary as well. 2. 3. 4. Periodically sampled and not 100% tested For an external clock generator, RESET duration is measured during the time in which RESET is asserted, VCC is valid, and the EXTAL input is active and valid. For internal oscillator, RESET duration is measured during the time in which RESET is asserted and VCC is valid. The specified timing reflects the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the crystal and other components connected to the oscillator and reflects worst case conditions. When the VCC is valid, but the other "required RESET duration" conditions (as specified above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the shortest possible duration. 2-12 DSP56364 Advance Information MOTOROLA Specifications Reset, Stop, Mode Select, and Interrupt Timing Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing6 (Continued) No. 5. Characteristics Expression Min Max Unit For an external clock generator, RESET duration is measured during the time in which RESET is asserted, VCC is valid, and the EXTAL input is active and valid. For internal oscillator, RESET duration is measured during the time in which RESET is asserted and VCC is valid. The specified timing reflects the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the crystal and other components connected to the oscillator and reflects worst case conditions. When the VCC is valid, but the other "required RESET duration" conditions (as specified above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the shortest possible duration. If PLL does not lose lock VCC = 3.3 V 0.16 V; TJ = 0C to + 105C, CL = 50 pF WS = number of wait states (measured in clock cycles, number of TC) Use expression to compute maximum value. VIH 6. 7. 8. 9. RESET 9 8 All Pins Reset Value 10 A0-A17 First Fetch AA0460 Figure 2-2. Reset Timing MOTOROLA DSP56364 Advance Information 2-13 Specifications Reset, Stop, Mode Select, and Interrupt Timing A0-A17 First Interrupt Instruction Execution/Fetch RD 20 WR 21 IRQA, IRQB, IRQD, NMI 17 19 a) First Interrupt Instruction Execution General Purpose I/O 18 IRQA, IRQB, IRQD, NMI b) General Purpose I/O AA0462 Figure 2-3. External Fast Interrupt Timing 2-14 DSP56364 Advance Information MOTOROLA Specifications Reset, Stop, Mode Select, and Interrupt Timing IRQA, IRQB, IRQD, NMI 15 IRQA, IRQB, IRQD, NMI 16 AA0463 Figure 2-4. External Interrupt Timing (Negative Edge-Triggered) RESET VIH 13 14 VIH VIH VIL MODA, MODB,MODD, PINIT VIL IRQA, IRQB, IRQD, NMI AA0465 Figure 2-5. Operating Mode Select Timing 24 IRQA 25 First Instruction Fetch AA0466 A0-A17 Figure 2-6. Recovery from Stop State Using IRQA MOTOROLA DSP56364 Advance Information 2-15 Specifications Reset, Stop, Mode Select, and Interrupt Timing 26 IRQA 25 A0-A17 First IRQA Interrupt Instruction Fetch AA0467 Figure 2-7. Recovery from Stop State Using IRQA Interrupt Service A0-A17 DMA Source Address RD WR 29 IRQA, IRQB, IRQD, NMI First Interrupt Instruction Execution AA1104 Figure 2-8. External Memory Access (DMA Source) Timing 2-16 DSP56364 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) EXTERNAL MEMORY EXPANSION PORT (PORT A) SRAM Timing Table 2-8. SRAM Read and Write Accesses3 No. Characteristics Symbol Expression1 (WS + 1) x TC - 4.0 [1 WS 3] tRC, tWC (WS + 2) x TC - 4.0 [4 WS 7] (WS + 3) x TC - 4.0 [WS 8] 101 Address and AA valid to WR assertion tAS 0.25 x TC - 2.0 [WS = 1] 0.75 x TC - 2.0 [2 WS 3] 1.25 x TC - 2.0 [WS 4] 102 WR assertion pulse width tWP Min 16.0 56.0 106.0 0.5 5.5 10.5 Max Unit -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns 100 Address valid and AA assertion pulse width 1.5 x TC - 4.0 [WS = 1] 11.0 All frequencies: WS x TC - 4.0 [2 WS 3] (WS - 0.5) x TC - 4.0 [WS 4] 16.0 31.0 -- ns MOTOROLA DSP56364 Advance Information 2-17 Specifications External Memory Expansion Port (Port A) Table 2-8. SRAM Read and Write Accesses3 (Continued) No. Characteristics WR deassertion to address not valid Symbol tWR Expression1 0.25 x TC - 2.0 [1 WS 3] 1.25 x TC - 2.0 [4 WS 7] 103 2.25 x TC - 2.0 [WS 8] All frequencies: 1.25 x TC - 4.0 [4 WS 7] 2.25 x TC - 4.0 [WS 8] 104 Address and AA valid to input data valid 105 RD assertion to input data valid 106 RD deassertion to data not valid (data hold time) tAA, tAC tOE tOHZ tAW tDS (tDW) tDH (WS + 0.75) x TC - 4.0 [WS 1] (WS - 0.25) x TC - 3.0 [WS 1] 0.25 x TC - 2.0 [1 WS 3] 1.25 x TC - 2.0 [4 WS 7] 2.25 x TC - 2.0 [WS 8] RD deassertion time 113 0.75 x TC - 4.0 [1 WS 3] 1.75 x TC - 4.0 [4 WS 7] 2.75 x TC - 4.0 [WS 8] (WS + 0.75) x TC - 7.0 [WS 1] (WS + 0.25) x TC - 7.0 [WS 1] Min 0.5 10.5 20.5 Max Unit -- -- -- ns ns ns 8.5 -- ns 18.5 -- -- 0.0 13.5 4.5 0.5 10.5 20.5 3.5 13.5 23.5 -- 10.5 5.5 -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns 107 Address valid to WR deassertion2 108 Data valid to WR deassertion (data setup time) Data hold time from WR deassertion 109 2-18 DSP56364 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) Table 2-8. SRAM Read and Write Accesses3 (Continued) No. Characteristics WR deassertion time Symbol Expression1 0.5 x TC - 4.0 [WS = 1] TC - 2.0 [2 WS 3] 114 2.5 x TC - 4.0 [4 WS 7] 3.5 x TC - 4.0 [WS 8] 115 Address valid to RD assertion 116 RD assertion pulse width RD deassertion to address not valid 117 0.5 x TC - 4.0 (WS + 0.25) x TC -4.0 0.25 x TC - 2.0 [1 WS 3] 1.25 x TC - 2.0 [4 WS 7] 2.25 x TC - 2.0 [WS 8] 118 TA setup before RD or WR deassertion4 119 TA hold after RD or WR deassertion Notes: 1. 2. 3. 4. Min 1.0 6.0 21.0 31.0 1.0 8.5 0.5 10.5 20.5 4.5 0 Max Unit -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns 0.25 x TC + 2.0 WS is the number of wait states specified in the BCR. Timings 100, 107 are guaranteed by design, not tested. All timings for 100 MHz are measured from 0.5 * Vcc to .05 * Vcc In the case of TA negation: timing 118 is relative to the deassertion edge of RD or WR were TA to remain active MOTOROLA DSP56364 Advance Information 2-19 Specifications External Memory Expansion Port (Port A) 100 A0-A17 AA0-AA1 113 RD 115 WR 104 119 TA D0-D7 Data In AA0468 116 117 105 106 118 Figure 2-9. SRAM Read Access 2-20 DSP56364 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) 100 A0-A17 AA0-AA3 107 101 WR 114 RD 119 TA 108 110 112 D0-D23 Data Out AA0469 102 103 118 111 109 Figure 2-10. SRAM Write Access MOTOROLA DSP56364 Advance Information 2-21 Specifications External Memory Expansion Port (Port A) DRAM Timing The selection guides provided in Figure 2-11. and Figure 2-14. should be used for primary selection only. Final selection should be based on the timing provided in the following tables. As an example, the selection guide suggests that 4 wait states must be used for 100 MHz operation when using Page Mode DRAM. However, by using the information in the appropriate table, a designer may choose to evaluate whether fewer wait states might be used by determining which timing prevents operation at 100 MHz, running the chip at a slightly lower frequency (e.g., 95 MHz), using faster DRAM (if it becomes available), and control factors such as capacitive and resistive load to improve overall system performance. DRAM Type (tRAC ns) 100 Note: This figure should be use for primary selection. For exact and detailed timings see the following tables. 80 70 60 50 40 66 80 100 120 Chip Frequency (MHz) 1 Wait States 2 Wait States 3 Wait States 4 Wait States AA047 Figure 2-11. DRAM Page Mode Wait States Selection Guide 2-22 DSP56364 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) Table 2-9. DRAM Page Mode Timings, One Wait State (Low-Power Applications)1, 2, 3 20 MHz6 No. Characteristics Symbol Expression Min Page mode cycle time for two consecutive accesses of the same direction 131 Page mode cycle time for mixed (read and write) accesses 132 133 134 135 136 137 CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) Last CAS assertion to RAS deassertion Previous CAS deassertion to RAS deassertion CAS assertion pulse width Last CAS deassertion to RAS deassertion4 * BRW[1:0] = 00 138 * BRW[1:0] = 01 * BRW[1:0] = 10 * BRW[1:0] = 11 139 140 141 142 CAS deassertion pulse width Column address valid to CAS assertion CAS assertion to column address not valid Last column address valid to RAS deassertion tCP tASC tCAH tRAL tPC 1.25 x TC TC - 7.5 1.5 x TC - 7.5 62.5 -- 41.7 -- 2 x TC Max Min Max 30 MHz6 Unit 100.0 -- 66.7 -- ns tCAC tAA tOFF tRSH tRHCP tCAS tCRP -- -- 0.0 42.5 67.5 -- -- -- -- -- -- -- 0.0 21.0 62.7 21.0 52.3 102.2 135.5 25.8 42.5 -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.75 x TC - 4.0 2 x TC - 4.0 0.75 x TC - 4.0 1.75 x TC - 6.0 33.5 96.0 33.5 81.5 3.25 x TC - 6.0 156.5 4.25 x TC - 6.0 206.5 6.25 x TC - 6.0 306.5 0.5 x TC - 4.0 0.5 x TC - 4.0 0.75 x TC - 4.0 2 x TC - 4.0 21.0 21.0 33.5 96.0 -- -- -- -- -- 202.1 12.7 12.7 21.0 62.7 MOTOROLA DSP56364 Advance Information 2-23 Specifications External Memory Expansion Port (Port A) Table 2-9. DRAM Page Mode Timings, One Wait State (Low-Power Applications)1, 2, 3 20 MHz6 No. Characteristics Symbol Expression Min 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Notes: 30 MHz6 Unit Min 21.2 4.6 12.5 45.5 54.0 54.0 4.3 21.0 29.0 46.0 -- 0.0 24.7 -- Max -- -- -- -- -- -- -- -- -- -- 25.8 -- -- 8.3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Max -- -- -- -- -- -- -- -- -- -- 42.5 -- -- 12.5 WR deassertion to CAS assertion CAS deassertion to WR assertion CAS assertion to WR deassertion WR assertion pulse width Last WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (Write) CAS assertion to data not valid (write) WR assertion to CAS assertion Last RD assertion to RAS deassertion RD assertion to data valid RD deassertion to data not valid 5 WR assertion to data active WR deassertion to data high impedance 1. 2. 3. 4. 5. 6. tRCS tRCH tWCH tWP tRWL tCWL tDS tDH tWCS tROH tGA tGZ 0.75 x TC - 3.8 0.25 x TC - 3.7 0.5 x TC - 4.2 1.5 x TC - 4.5 1.75 x TC - 4.3 1.75 x TC - 4.3 0.25 x TC - 4.0 0.75 x TC - 4.0 TC - 4.3 1.5 x TC - 4.0 TC - 7.5 33.7 8.8 20.8 70.5 83.2 83.2 8.5 33.5 45.7 71.0 -- 0.0 0.75 x TC - 0.3 0.25 x TC 37.2 -- The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 2 x TC for read-after-read or write-after-write sequences). BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. Reduced DSP clock speed allows use of Page Mode DRAM with one Wait state (See Figure 2-14.). 2-24 DSP56364 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) Table 2-10. DRAM Page Mode Timings, Two Wait States1, 2, 3, 7 66 MHz No. Characteristics Page mode cycle time for two consecutive accesses of the same direction 131 Page mode cycle time for mixed (read and write) accesses 132 CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) Last CAS assertion to RAS deassertion Previous CAS deassertion to RAS deassertion tPC 1.25 x TC 1.5 x TC - 7.5 1.5 x TC - 6.5 2.5 x TC - 7.5 2.5 x TC - 6.5 41.1 -- -- -- -- 0.0 1.75 x TC - 4.0 3.25 x TC - 4.0 1.5 x TC - 4.0 2.0 x TC - 6.0 3.5 x TC - 6.0 4.5 x TC - 6.0 6.5 x TC - 6.0 tCP tASC tCAH 1.25 x TC - 4.0 TC - 4.0 1.75 x TC - 4.0 22.5 45.2 18.7 24.4 47.2 62.4 92.8 14.9 11.2 22.5 -- 15.2 -- 30.4 -- -- -- -- -- -- -- -- -- -- -- -- 34.4 -- -- -- -- 0.0 17.9 36.6 14.8 19.0 37.8 50.3 75.3 11.6 8.5 17.9 -- -- 12.3 -- 24.8 -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Symbol Expression Min 2 x TC Max Min Max 80 MHz Unit 45.4 -- 37.5 -- ns tCAC 133 tAA 134 135 136 tOFF tRSH tRHCP tCAS tCRP 137 CAS assertion pulse width Last CAS deassertion to RAS deassertion5 * BRW[1:0] = 00 138 * BRW[1:0] = 01 * BRW[1:0] = 10 * BRW[1:0] = 11 139 140 141 CAS deassertion pulse width Column address valid to CAS assertion CAS assertion to column address not valid MOTOROLA DSP56364 Advance Information 2-25 Specifications External Memory Expansion Port (Port A) Table 2-10. DRAM Page Mode Timings, Two Wait States1, 2, 3, 7 (Continued) 66 MHz No. Characteristics Last column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR assertion CAS assertion to WR deassertion Symbol Expression Min 142 143 144 145 tRAL tRCS tRCH tWCH tWP tRWL tCWL 3 x TC - 4.0 1.25 x TC - 3.8 0.5 x TC - 3.7 1.5 x TC - 4.2 2.5 x TC - 4.5 2.75 x TC - 4.3 2.5 x TC - 4.3 0.25 x TC - 3.7 0.25 x TC - 3.0 1.75 x TC - 4.0 TC - 4.3 2.5 x TC - 4.0 1.75 x TC - 7.5 153 RD assertion to data valid tGA 1.75 x TC - 6.5 154 RD deassertion to data not valid6 tGZ 0.75 x TC - 0.3 0.25 x TC -- 0.0 11.1 -- -- -- -- 3.8 -- 0.0 9.1 -- 15.4 -- -- 3.1 ns ns ns ns 41.5 15.1 3.9 18.5 33.5 33.4 33.6 0.1 -- 22.5 10.9 33.9 -- Max -- -- -- -- -- -- -- -- -- -- -- -- 19.0 Min 33.5 11.8 2.6 14.6 26.8 26.8 27.0 -- 0.1 17.9 8.2 27.3 -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns 80 MHz Unit 146 WR assertion pulse width 147 148 Last WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) WR assertion to CAS assertion Last RD assertion to RAS deassertion 149 tDS 150 151 152 tDH tWCS tROH 155 WR assertion to data active 156 WR deassertion to data high impedance 2-26 DSP56364 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) Table 2-10. DRAM Page Mode Timings, Two Wait States1, 2, 3, 7 (Continued) 66 MHz No. Notes: 1. 2. 3. 4. 5. 6. 7. 80 MHz Unit Min Max Characteristics Symbol Expression Min Max The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56364. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 3 x TC for read-after-read or write-after-write sequences). BRW[1:0] (DRAM Control Register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. There are no DRAMs fast enough to fit to two wait states Page mode @ 100MHz (See Figure 2-11.) Table 2-11. DRAM Page Mode Timings, Three Wait States1, 2, 3 No. Characteristics Page mode cycle time for two consecutive accesses of the same direction 131 Page mode cycle time for mixed (read and write) accesses 132 CAS assertion to data valid (read) 133 Column address valid to data valid (read) 134 CAS deassertion to data not valid (read hold time) 135 Last CAS assertion to RAS deassertion 136 Previous CAS deassertion to RAS deassertion 137 CAS assertion pulse width Last CAS deassertion to RAS assertion5 * BRW[1:0] = 00 138 * BRW[1:0] = 01 * BRW[1:0] = 10 * BRW[1:0] = 11 139 CAS deassertion pulse width 140 Column address valid to CAS assertion 141 CAS assertion to column address not valid tCP tASC tCAH tPC 1.25 x TC tCAC tAA tOFF tRSH tRHCP tCAS tCRP 2 x TC - 7.0 3 x TC - 7.0 35.0 -- -- 0.0 2.5 x TC - 4.0 21.0 4.5 x TC - 4.0 41.0 2 x TC - 4.0 2.25 x TC - 6.0 3.75 x TC - 6.0 16.0 -- -- -- 13.0 23.0 -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns Symbol Expression 2 x TC Min Max Unit 40.0 -- ns 4.75 x TC - 6.0 41.5 6.75 x TC - 6.0 61.5 1.5 x TC - 4.0 11.0 TC - 4.0 6.0 2.5 x TC - 4.0 21.0 MOTOROLA DSP56364 Advance Information 2-27 Specifications External Memory Expansion Port (Port A) Table 2-11. DRAM Page Mode Timings, Three Wait States1, 2, 3 (Continued) No. Characteristics Symbol tRAL tRCS tRCH tWCH tWP tRWL tCWL tDS tDH tWCS tROH tGA tGZ Expression 4 x TC - 4.0 Min Max Unit 36.0 -- -- -- -- -- -- -- -- -- -- -- 18.0 -- -- 2.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 142 Last column address valid to RAS deassertion 143 WR deassertion to CAS assertion 144 CAS deassertion to WR assertion 145 CAS assertion to WR deassertion 146 WR assertion pulse width 147 Last WR assertion to RAS deassertion 148 WR assertion to CAS deassertion 149 Data valid to CAS assertion (write) 150 CAS assertion to data not valid (write) 151 WR assertion to CAS assertion 152 Last RD assertion to RAS deassertion 153 RD assertion to data valid 154 RD deassertion to data not valid6 155 WR assertion to data active 156 WR deassertion to data high impedance Notes: 1. 2. 3. 4. 5. 6. 1.25 x TC - 4.0 8.5 0.75 x TC - 4.0 3.5 2.25 x TC - 4.2 18.3 3.5 x TC - 4.5 30.5 3.75 x TC - 4.3 33.2 3.25 x TC - 4.3 28.2 0.5 x TC - 4.0 1.0 2.5 x TC - 4.0 21.0 1.25 x TC - 4.3 8.2 3.5 x TC - 4.0 31.0 2.5 x TC - 7.0 -- 0.0 0.75 x TC - 0.3 7.2 0.25 x TC -- The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56364. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 4 x TC for read-after-read or write-after-write sequences). BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of page-access. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. 2-28 DSP56364 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) Table 2-12. DRAM Page Mode Timings, Four Wait States1, 2, 3 No. Characteristics Page mode cycle time for two consecutive accesses of the same direction. 131 Page mode cycle time for mixed (read and write) accesses 132 CAS assertion to data valid (read) 133 Column address valid to data valid (read) 134 CAS deassertion to data not valid (read hold time) 135 Last CAS assertion to RAS deassertion 136 Previous CAS deassertion to RAS deassertion 137 CAS assertion pulse width Last CAS deassertion to RAS assertion5 * BRW[1:0] = 00 138 * BRW[1:0] = 01 * BRW[1:0] = 10 * BRW[1:0] = 11 139 CAS deassertion pulse width 140 Column address valid to CAS assertion 141 CAS assertion to column address not valid 142 Last column address valid to RAS deassertion 143 WR deassertion to CAS assertion 144 CAS deassertion to WR assertion 145 CAS assertion to WR deassertion 146 WR assertion pulse width 147 Last WR assertion to RAS deassertion 148 WR assertion to CAS deassertion 149 Data valid to CAS assertion (write) 150 CAS assertion to data not valid (write) 151 WR assertion to CAS assertion tCP tASC tCAH tRAL tRCS tRCH tWCH tWP tRWL tCWL tDS tDH tWCS tPC 1.25 x TC tCAC tAA tOFF tRSH tRHCP tCAS tCRP 3.5 x TC - 4.0 6 x TC - 4.0 2.5 x TC - 4.0 2.75 x TC - 6.0 4.25 x TC - 6.0 2.75 x TC - 7.0 3.75 x TC - 7.0 45.0 -- -- 0.0 31.0 56.0 21.0 -- -- -- 20.5 30.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Symbol Expression 2 x TC Min Max 50.0 -- ns 5.25 x TC - 6.0 46.5 7.25 x TC - 6.0 66.5 2 x TC - 4.0 TC - 4.0 3.5 x TC - 4.0 5 x TC - 4.0 1.25 x TC - 4.0 1.25 x TC - 4.0 16.0 6.0 31.0 46.0 8.5 8.5 3.25 x TC - 4.2 28.3 4.5 x TC - 4.5 40.5 4.75 x TC - 4.3 43.2 3.75 x TC - 4.3 33.2 0.5 x TC - 4.0 3.5 x TC - 4.0 1.25 x TC - 4.3 1.0 31.0 8.2 MOTOROLA DSP56364 Advance Information 2-29 Specifications External Memory Expansion Port (Port A) Table 2-12. DRAM Page Mode Timings, Four Wait States1, 2, 3 (Continued) No. Characteristics Symbol tROH tGA tGZ 0.75 x TC - 0.3 0.25 x TC Expression 4.5 x TC - 4.0 3.25 x TC - 7.0 Min Max 41.0 -- 0.0 7.2 -- -- 25.5 -- -- 2.5 ns ns ns ns ns 152 Last RD assertion to RAS deassertion 153 RD assertion to data valid 154 RD deassertion to data not valid6 155 WR assertion to data active 156 WR deassertion to data high impedance Notes: 1. 2. 3. 4. 5. 6. The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56364. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 3 x TC for read-after-read or write-after-write sequences). BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. 2-30 DSP56364 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) RAS 136 131 CAS 137 140 141 A0-A17 Row Add Column Address Column Address 135 139 138 142 Last Column Address 151 145 WR 146 RD 155 144 143 147 148 156 150 149 D0-D7 Data Out Data Out Data Out AA0473 Figure 2-12. DRAM Page Mode Write Accesses MOTOROLA DSP56364 Advance Information 2-31 Specifications External Memory Expansion Port (Port A) RAS 136 131 CAS 137 140 A0-A17 Row Add Column Address 135 139 141 Column Address 138 142 Last Column Address 143 WR 132 133 153 RD 134 154 D0-D7 Data In Data In Data In AA0474 152 Figure 2-13. DRAM Page Mode Read Accesses 2-32 DSP56364 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) DRAM Type (tRAC ns) Note: This figure should be use for primary selection. For exact and detailed timings see the following tables. 100 80 70 60 50 40 66 80 100 120 11 Wait States 15 Wait States Chip Frequency (MHz) 4 Wait States 8 Wait States AA0475 Figure 2-14. DRAM Out-of-Page Wait States Selection Guide Table 2-13. DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2 No. Characteristics3 Random read or write cycle time RAS assertion to data valid (read) CAS assertion to data valid (read) Column address valid to data valid (read) Symbol Expression 20 MHz4 Min 157 158 159 160 tRC tRAC tCAC tAA 5 x TC 2.75 x TC - 7.5 1.25 x TC - 7.5 1.5 x TC - 7.5 250.0 -- -- -- Max -- 130.0 55.0 67.5 30 MHz4 Min 166.7 -- -- -- Max -- 84.2 34.2 42.5 ns ns ns ns Unit MOTOROLA DSP56364 Advance Information 2-33 Specifications External Memory Expansion Port (Port A) Table 2-13. DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2 (Continued) No. Characteristics3 CAS deassertion to data not valid (read hold time) RAS deassertion to RAS assertion Symbol Expression 20 MHz4 Min 161 162 tOFF tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tCP tASR tRAH tASC tCAH tAR tRAL tRCS tRCH 1.75 x TC - 4.0 3.25 x TC - 4.0 1.75 x TC - 4.0 2.75 x TC - 4.0 1.25 x TC - 4.0 1.5 x TC 2 1.25 x TC 2 2.25 x TC - 4.0 1.75 x TC - 4.0 1.75 x TC - 4.0 1.25 x TC - 4.0 0.25 x TC - 4.0 1.75 x TC - 4.0 3.25 x TC - 4.0 2 x TC - 4.0 1.5 x TC - 3.8 0.75 x TC - 3.7 0.0 83.5 158.5 83.5 133.5 58.5 73.0 60.5 108.5 83.5 83.5 58.5 8.5 83.5 158.5 96.0 71.2 33.8 Max -- -- -- -- -- -- 77.0 64.5 -- -- -- -- -- -- -- -- -- -- 30 MHz4 Min 0.0 54.3 104.3 54.3 87.7 37.7 48.0 39.7 71.0 54.3 54.3 37.7 4.3 54.3 104.3 62.7 46.2 21.3 Max -- -- -- -- -- -- 52.0 43.7 -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit 163 RAS assertion pulse width 164 165 CAS assertion to RAS deassertion RAS assertion to CAS deassertion 166 CAS assertion pulse width 167 168 169 RAS assertion to CAS assertion RAS assertion to column address valid CAS deassertion to RAS assertion 170 CAS deassertion pulse width 171 172 173 174 175 176 177 178 Row address valid to RAS assertion RAS assertion to row address not valid Column address valid to CAS assertion CAS assertion to column address not valid RAS assertion to column address not valid Column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR assertion 2-34 DSP56364 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) Table 2-13. DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2 (Continued) No. Characteristics3 RAS deassertion to WR assertion CAS assertion to WR deassertion RAS assertion to WR deassertion Symbol Expression 20 MHz4 Min 179 180 181 tRRH tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tWCS tCSR tRPC tROH tGA tGZ 0.75 x TC - 0.3 0.25 x TC 0.25 x TC - 3.7 1.5 x TC - 4.2 3 x TC - 4.2 4.5 x TC - 4.5 4.75 x TC - 4.3 4.25 x TC - 4.3 2.25 x TC - 4.0 1.75 x TC - 4.0 3.25 x TC - 4.0 3 x TC - 4.3 0.5 x TC - 4.0 1.25 x TC - 4.0 4.5 x TC - 4.0 4 x TC - 7.5 8.8 70.8 145.8 220.5 233.2 208.2 108.5 83.5 158.5 145.7 21.0 58.5 221.0 -- 0.0 37.2 -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- 192.5 -- -- 12.5 30 MHz4 Min 4.6 45.8 95.8 145.5 154.0 137.4 71.0 54.3 104.3 95.7 12.7 37.7 146.0 -- 0.0 24.7 -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- 125.8 -- -- 8.3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit 182 WR assertion pulse width 183 184 185 186 187 WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) RAS assertion to data not valid (write) 188 WR assertion to CAS assertion 189 190 191 CAS assertion to RAS assertion (refresh) RAS deassertion to CAS assertion (refresh) RD assertion to RAS deassertion 192 RD assertion to data valid 193 RD deassertion to data not valid3 194 WR assertion to data active 195 WR deassertion to data high impedance MOTOROLA DSP56364 Advance Information 2-35 Specifications External Memory Expansion Port (Port A) Table 2-13. DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2 (Continued) No. Notes: 1. 2. 3. 4. Characteristics3 Symbol Expression 20 MHz4 Min Max 30 MHz4 Min Max Unit The number of wait states for out of page access is specified in the DCR. The refresh period is specified in the DCR. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. Reduced DSP clock speed allows use of DRAM out-of-page access with four Wait states (See Figure 2-17.). Table 2-14. DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2 66 MHz No. Characteristics4 Random read or write cycle time RAS assertion to data valid (read) CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) RAS deassertion to RAS assertion Symbol Expression3 Min 157 tRC 9 x TC 4.75 x TC - 7.5 4.75 x TC - 6.5 2.25 x TC - 7.5 2.25 x TC - 6.5 3 x TC - 7.5 3 x TC - 6.5 136.4 -- -- -- -- -- -- 0.0 3.25 x TC - 4.0 5.75 x TC - 4.0 3.25 x TC - 4.0 4.75 x TC - 4.0 2.25 x TC - 4.0 2.5 x TC 2 45.2 83.1 45.2 68.0 30.1 35.9 Max -- 64.5 -- 26.6 -- 40.0 -- -- -- -- -- -- -- 39.9 Min 112.5 -- -- -- -- -- -- 0.0 36.6 67.9 36.6 55.5 24.1 29.3 Max -- -- 52.9 -- 21.6 -- 31.0 -- -- -- -- -- -- 33.3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 80 MHz Unit 158 tRAC 159 tCAC 160 tAA 161 162 tOFF tRP tRAS tRSH tCSH tCAS tRCD 163 RAS assertion pulse width 164 165 CAS assertion to RAS deassertion RAS assertion to CAS deassertion 166 CAS assertion pulse width 167 RAS assertion to CAS assertion 2-36 DSP56364 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) Table 2-14. DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2 (Continued) 66 MHz No. Characteristics4 RAS assertion to column address valid CAS deassertion to RAS assertion Symbol Expression3 Min 168 169 tRAD tCRP tCP tASR tRAH tASC tCAH tAR tRAL tRCS tRCH 1.75 x TC 2 4.25 x TC - 4.0 2.75 x TC - 4.0 3.25 x TC - 4.0 1.75 x TC - 4.0 0.75 x TC - 4.0 3.25 x TC - 4.0 5.75 x TC - 4.0 4 x TC - 4.0 2 x TC - 3.8 1.25 x TC - 3.7 0.25 x TC - 3.7 0.25 x TC - 3.0 3 x TC - 4.2 5.5 x TC - 4.2 8.5 x TC - 4.5 8.75 x TC - 4.3 7.75 x TC - 4.3 24.5 59.8 37.7 45.2 22.5 7.4 45.2 83.1 56.6 26.5 15.2 0.1 -- 41.3 79.1 124.3 128.3 113.1 Max 28.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Min 19.9 49.1 30.4 36.6 17.9 5.4 36.6 67.9 46.0 21.2 11.9 -- 0.1 33.3 64.6 101.8 105.1 92.6 Max 23.9 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 80 MHz Unit 170 CAS deassertion pulse width 171 172 173 174 175 176 177 178 Row address valid to RAS assertion RAS assertion to row address not valid Column address valid to CAS assertion CAS assertion to column address not valid RAS assertion to column address not valid Column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR5 assertion RAS deassertion to WR5 assertion CAS assertion to WR deassertion RAS assertion to WR deassertion 179 tRRH 180 181 tWCH tWCR tWP tRWL tCWL 182 WR assertion pulse width 183 184 WR assertion to RAS deassertion WR assertion to CAS deassertion MOTOROLA DSP56364 Advance Information 2-37 Specifications External Memory Expansion Port (Port A) Table 2-14. DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2 (Continued) 66 MHz No. Characteristics4 Data valid to CAS assertion (write) CAS assertion to data not valid (write) RAS assertion to data not valid (write) Symbol Expression3 Min 185 186 187 tDS tDH tDHR tWCS tCSR tRPC tROH 4.75 x TC - 4.0 3.25 x TC - 4.0 5.75 x TC - 4.0 5.5 x TC - 4.3 1.5 x TC - 4.0 1.75 x TC - 4.0 8.5 x TC - 4.0 7.5 x TC - 7.5 7.5 x TC - 6.5 0.0 0.75 x TC - 0.3 0.25 x TC 68.0 45.2 83.1 79.0 18.7 22.5 124.8 -- -- 0.0 11.1 -- Max -- -- -- -- -- -- -- 106.1 -- -- -- 3.8 Min 55.4 36.6 67.9 64.5 14.8 17.9 102.3 -- -- 0.0 9.1 -- Max -- -- -- -- -- -- -- -- 87.3 -- -- 3.1 ns ns ns ns ns ns ns ns ns ns ns ns 80 MHz Unit 188 WR assertion to CAS assertion 189 190 191 CAS assertion to RAS assertion (refresh) RAS deassertion to CAS assertion (refresh) RD assertion to RAS deassertion 192 RD assertion to data valid RD deassertion to data not valid4 tGA 193 tGZ 194 WR assertion to data active 195 WR deassertion to data high impedance 1. 2. 3. 4. 5. Notes: The number of wait states for out-of-page access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56364. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. Either tRCH or tRRH must be satisfied for read cycles. 2-38 DSP56364 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) Table 2-15. DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2 No. Characteristics4 Symbol tRC tRAC tCAC tAA tOFF tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tCP tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH tWCH tWCR tWP 4.25 x TC - 4.0 7.75 x TC - 4.0 5.25 x TC - 4.0 6.25 x TC - 4.0 3.75 x TC - 4.0 2.5 x TC 4.0 1.75 x TC 4.0 5.75 x TC - 4.0 4.25 x TC - 4.0 4.25 x TC - 4.0 1.75 x TC - 4.0 0.75 x TC - 4.0 5.25 x TC - 4.0 7.75 x TC - 4.0 6 x TC - 4.0 3.0 x TC - 4.0 1.75 x TC - 4.0 0.25 x TC - 2.0 5 x TC - 4.2 7.5 x TC - 4.2 Expression3 12 x TC 6.25 x TC - 7.0 3.75 x TC - 7.0 4.5 x TC - 7.0 Min 120.0 -- -- -- 0.0 38.5 73.5 48.5 58.5 33.5 21.0 13.5 53.5 38.5 38.5 13.5 3.5 48.5 73.5 56.0 26.0 13.5 0.5 45.8 70.8 Max -- 55.5 30.5 38.0 -- -- -- -- -- -- 29.0 21.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 157 Random read or write cycle time 158 RAS assertion to data valid (read) 159 CAS assertion to data valid (read) 160 Column address valid to data valid (read) 161 CAS deassertion to data not valid (read hold time) 162 RAS deassertion to RAS assertion 163 RAS assertion pulse width 164 CAS assertion to RAS deassertion 165 RAS assertion to CAS deassertion 166 CAS assertion pulse width 167 RAS assertion to CAS assertion 168 RAS assertion to column address valid 169 CAS deassertion to RAS assertion 170 CAS deassertion pulse width 171 Row address valid to RAS assertion 172 RAS assertion to row address not valid 173 Column address valid to CAS assertion 174 CAS assertion to column address not valid 175 RAS assertion to column address not valid 176 Column address valid to RAS deassertion 177 WR deassertion to CAS assertion 178 CAS deassertion to WR5 assertion 179 RAS deassertion to WR5 assertion 180 CAS assertion to WR deassertion 181 RAS assertion to WR deassertion 182 WR assertion pulse width 11.5 x TC - 4.5 110.5 MOTOROLA DSP56364 Advance Information 2-39 Specifications External Memory Expansion Port (Port A) Table 2-15. DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2 (Continued) No. Characteristics4 Symbol tRWL tCWL tDS tDH tDHR tWCS tCSR tRPC tROH tGA tGZ 0.75 x TC - 0.3 0.25 x TC Expression3 Min Max -- -- -- -- -- -- -- -- -- 93.0 -- -- 2.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 183 WR assertion to RAS deassertion 184 WR assertion to CAS deassertion 185 Data valid to CAS assertion (write) 186 CAS assertion to data not valid (write) 187 RAS assertion to data not valid (write) 188 WR assertion to CAS assertion 189 CAS assertion to RAS assertion (refresh) 190 RAS deassertion to CAS assertion (refresh) 191 RD assertion to RAS deassertion 192 RD assertion to data valid 193 RD deassertion to data not valid4 194 WR assertion to data active 195 WR deassertion to data high impedance Notes: 1. 2. 3. 4. 5. 11.75 x TC - 4.3 113.2 10.25 x TC - 4.3 103.2 5.75 x TC - 4.0 5.25 x TC - 4.0 7.75 x TC - 4.0 6.5 x TC - 4.3 1.5 x TC - 4.0 2.75 x TC - 4.0 53.5 48.5 73.5 60.7 11.0 23.5 11.5 x TC - 4.0 111.0 10 x TC - 7.0 -- 0.0 7.2 -- The number of wait states for out-of-page access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56364. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. Either tRCH or tRRH must be satisfied for read cycles. 2-40 DSP56364 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) Table 2-16. DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2 No. Characteristics3 Symbol tRC tRAC tCAC tAA tOFF tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tCP tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH tWCH tWCR Expression 16 x TC 8.25 x TC - 5.7 4.75 x TC - 5.7 5.5 x TC - 5.7 0.0 6.25 x TC - 4.0 9.75 x TC - 4.0 6.25 x TC - 4.0 8.25 x TC - 4.0 4.75 x TC - 4.0 3.5 x TC 2 2.75 x TC 2 7.75 x TC - 4.0 6.25 x TC - 4.0 6.25 x TC - 4.0 2.75 x TC - 4.0 0.75 x TC - 4.0 6.25 x TC - 4.0 9.75 x TC - 4.0 7 x TC - 4.0 5 x TC - 3.8 1.75 x TC - 3.7 0.25 x TC - 2.0 6 x TC - 4.2 9.5 x TC - 4.2 Min 160.0 -- -- -- 0.0 58.5 93.5 58.5 78.5 43.5 33.0 25.5 73.5 58.5 58.5 23.5 3.5 58.5 93.5 66.0 46.2 13.8 0.5 55.8 90.8 Max -- 76.8 41.8 49.3 -- -- -- -- -- -- 37.0 29.5 -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 157 Random read or write cycle time 158 RAS assertion to data valid (read) 159 CAS assertion to data valid (read) 160 Column address valid to data valid (read) 161 CAS deassertion to data not valid (read hold time) 162 RAS deassertion to RAS assertion 163 RAS assertion pulse width 164 CAS assertion to RAS deassertion 165 RAS assertion to CAS deassertion 166 CAS assertion pulse width 167 RAS assertion to CAS assertion 168 RAS assertion to column address valid 169 CAS deassertion to RAS assertion 170 CAS deassertion pulse width 171 Row address valid to RAS assertion 172 RAS assertion to row address not valid 173 Column address valid to CAS assertion 174 CAS assertion to column address not valid 175 RAS assertion to column address not valid 176 Column address valid to RAS deassertion 177 WR deassertion to CAS assertion 178 CAS deassertion to WR5 assertion 179 RAS deassertion to WR5 assertion 180 CAS assertion to WR deassertion 181 RAS assertion to WR deassertion MOTOROLA DSP56364 Advance Information 2-41 Specifications External Memory Expansion Port (Port A) Table 2-16. DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2 (Continued) No. Characteristics3 Symbol tWP tRWL tCWL tDS tDH tDHR tWCS tCSR tRPC tROH tGA tGZ 0.75 x TC - 0.3 0.25 x TC Expression 15.5 x TC - 4.5 15.75 x TC - 4.3 14.25 x TC - 4.3 8.75 x TC - 4.0 6.25 x TC - 4.0 9.75 x TC - 4.0 9.5 x TC - 4.3 1.5 x TC - 4.0 4.75 x TC - 4.0 15.5 x TC - 4.0 14 x TC - 5.7 Min 150.5 153.2 138.2 83.5 58.5 93.5 90.7 11.0 43.5 151.0 -- 0.0 7.2 -- Max -- -- -- -- -- -- -- -- -- -- 134.3 -- -- 2.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 182 WR assertion pulse width 183 WR assertion to RAS deassertion 184 WR assertion to CAS deassertion 185 Data valid to CAS assertion (write) 186 CAS assertion to data not valid (write) 187 RAS assertion to data not valid (write) 188 WR assertion to CAS assertion 189 CAS assertion to RAS assertion (refresh) 190 RAS deassertion to CAS assertion (refresh) 191 RD assertion to RAS deassertion 192 RD assertion to data valid 193 RD deassertion to data not valid3 194 WR assertion to data active 195 WR deassertion to data high impedance Notes: 1. 2. 3. 4. The number of wait states for out-of-page access is specified in the DCR. The refresh period is specified in the DCR. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. Either tRCH or tRRH must be satisfied for read cycles. 2-42 DSP56364 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) 157 162 RAS 167 169 170 CAS 171 173 174 175 A0-A17 Row Address Column Address 163 165 162 164 168 166 172 177 191 WR 160 159 RD 158 192 176 179 168 193 161 Data In AA0476 D0-D7 Figure 2-15. DRAM Out-of-Page Read Access MOTOROLA DSP56364 Advance Information 2-43 Specifications External Memory Expansion Port (Port A) 157 162 RAS 167 169 168 170 CAS 171 173 172 176 A0-A17 Row Address 181 175 188 WR 182 184 183 RD 185 194 D0-D7 Data Out AA0477 163 165 164 162 166 174 Column Address 180 187 186 195 Figure 2-16. DRAM Out-of-Page Write Access 2-44 DSP56364 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) 157 162 RAS 190 170 CAS 165 163 162 189 177 WR AA0478 Figure 2-17. DRAM Refresh Access MOTOROLA DSP56364 Advance Information 2-45 Specifications Serial Host Interface SPI Protocol Timing SERIAL HOST INTERFACE SPI PROTOCOL TIMING Table 2-17. Serial Host Interface SPI Protocol Timing No. Characteristics Mode Filter Mode Bypassed Tolerable spike width on clock or data 140 in -- Narrow Wide Bypassed Minimum serial clock cycle = 141 tSPICC(min) Master Narrow Wide Bypassed Master 142 Serial clock high period Bypassed Slave Narrow Wide Bypassed Master 143 Serial clock low period Bypassed Slave Narrow Wide Master 144 Serial clock rise/fall time Slave -- -- -- 2000 ns -- Narrow Wide Narrow Wide Expression -- -- -- 6xTC+46 6xTC+152 6xTC+223 0.5xtSPICC -10 0.5xtSPICC -10 0.5xtSPICC -10 2.5xTC+12 2.5xTC+102 2.5xTC+189 0.5xtSPICC -10 0.5xtSPICC -10 0.5xtSPICC -10 2.5xTC+12 2.5xTC+102 2.5xTC+189 -- Min -- -- -- 106 212 283 43 96 131 37 127 214 43 96 131 37 127 214 -- Max 0 50 100 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2-46 DSP56364 Advance Information MOTOROLA Specifications Serial Host Interface SPI Protocol Timing Table 2-17. Serial Host Interface SPI Protocol Timing (Continued) No. Characteristics Mode Filter Mode Bypassed SS assertion to first SCK edge CPHA = 0 146 Slave CPHA = 1 Bypassed Narrow Wide Bypassed 147 Last SCK edge to SS not asserted Slave Narrow Wide Bypassed Data input valid to SCK edge (data 148 input set-up time) Master /Slave Narrow Wide Bypassed SCK last sampling edge to data input Master 149 not valid /Slave 150 SS assertion to data out active 151 SS deassertion to data high impedance Slave Slave Narrow Wide -- -- Bypassed SCK edge to data out valid 152 (data out delay time) Master /Slave Narrow Wide Bypassed SCK edge to data out not valid 153 (data out hold time) SS assertion to data out valid (CPHA = 0) Master /Slave Narrow Wide 154 Slave -- 10 0 0 12 102 189 0 MAX{(20-TC), 0} MAX{(40-TC), 0} 2.5xTC+10 2.5xTC+30 2.5xTC+50 2 9 2xTC+33 2xTC+123 2xTC+210 TC+5 TC+55 TC+106 TC+33 10 0 0 12 102 189 0 10 30 35 55 75 2 -- -- -- -- 15 65 116 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 9 53 143 230 -- -- -- 43 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Narrow Slave Wide 0 0 -- ns Expression 3.5xTC+15 0 Min 50 0 Max -- -- Unit ns ns MOTOROLA DSP56364 Advance Information 2-47 Specifications Serial Host Interface SPI Protocol Timing Table 2-17. Serial Host Interface SPI Protocol Timing (Continued) No. Characteristics Mode Filter Mode Bypassed First SCK sampling edge to HREQ 157 output deassertion Slave Narrow Wide Bypassed Last SCK sampling edge to HREQ 158 output not deasserted (CPHA = 1) SS deassertion to HREQ output not deasserted (CPHA = 0) SS deassertion pulse width (CPHA = 0) Slave Narrow Wide 159 160 Slave Slave -- -- Bypassed 161 HREQ in assertion to first SCK edge Master Narrow Wide HREQ in deassertion to last SCK 162 sampling edge (HREQ in set-up time) Master (CPHA = 1) First SCK edge to HREQ in not 163 asserted (HREQ in hold time) Note: Periodically sampled, not 100% tested Expression 2.5xTC+30 2.5xTC+120 2.5xTC+217 2.5xTC+30 2.5xTC+80 2.5xTC+136 2.5xTC+30 TC+6 0.5 x tSPICC + 2.5xTC+43 0.5 xtSPICC + 2.5xTC+43 0.5 xtSPICC + 2.5xTC+43 0 Min -- -- -- 55 105 161 55 16 121 174 209 Max 55 145 242 -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns -- 0 -- ns Master -- 0 0 -- ns 2-48 DSP56364 Advance Information MOTOROLA Specifications Serial Host Interface SPI Protocol Timing SS (Input) 143 142 SCK (CPOL = 0) (Output) 142 143 SCK (CPOL = 1) (Output) 148 149 MISO (Input) MSB Valid 141 144 144 141 144 144 148 LSB Valid 149 152 MOSI (Output) 161 163 HREQ (Input) MSB 153 LSB AA0271 Figure 2-18. SPI Master Timing (CPHA = 0) MOTOROLA DSP56364 Advance Information 2-49 Specifications Serial Host Interface SPI Protocol Timing SS (Input) 143 142 SCK (CPOL = 0) (Output) 142 143 SCK (CPOL = 1) (Output) 148 149 MISO (Input) MSB Valid LSB Valid 141 144 144 141 144 144 148 149 152 MOSI (Output) 161 163 HREQ (Input) MSB 162 153 LSB AA0272 Figure 2-19. SPI Master Timing (CPHA = 1) 2-50 DSP56364 Advance Information MOTOROLA Specifications Serial Host Interface SPI Protocol Timing SS (Input) 143 142 SCK (CPOL = 0) (Input) 146 142 143 SCK (CPOL = 1) (Input) 154 150 MISO (Output) 148 149 MOSI (Input) MSB Valid LSB Valid 141 144 144 160 147 141 144 144 152 153 MSB 153 151 LSB 148 149 157 HREQ (Output) 159 AA0273 Figure 2-20. SPI Slave Timing (CPHA = 0) MOTOROLA DSP56364 Advance Information 2-51 Specifications Serial Host Interface SPI Protocol Timing SS (Input) 143 142 SCK (CPOL = 0) (Input) 146 142 143 SCK (CPOL = 1) (Input) 152 150 MISO (Output) 148 149 MOSI (Input) MSB Valid LSB Valid 141 144 144 147 144 144 152 153 151 LSB 148 149 MSB 157 HREQ (Output) 158 AA0274 Figure 2-21. SPI Slave Timing (CPHA = 1) 2-52 DSP56364 Advance Information MOTOROLA Specifications Serial Host Interface (SHI) I 2C Protocol Timing SERIAL HOST INTERFACE (SHI) I2C PROTOCOL TIMING Table 2-18. SHI I2C Protocol Timing Standard I2C* StandardMode Min Tolerable spike width on SCL or SDA Filters bypassed Narrow filters enabled Wide filters enabled 171 SCL clock frequency 172 Bus free time 173 Start condition set-up time 174 Start condition hold time 175 SCL low period 176 SCL high period 177 SCL and SDA rise time 178 SCL and SDA fall time 179 Data set-up time 180 Data hold time 181 Stop condition set-up time 182 Capacitive load for each line DSP clock frequency Filters bypassed 183 Narrow filters enabled Wide filters enabled FDSP 10.6 11.8 13.1 -- -- -- 28.5 39.7 61.0 -- -- -- MHz MHz MHz FSCL TBUF TSU;STA THD;STA TLOW THIGH TR TF TSU;DAT THD;DAT TSU;STO Cb -- -- -- -- -- 4.7 4.7 4.0 4.7 4.0 -- -- 250 0.0 4.0 -- 0 50 100 100 -- -- -- -- -- 1000 300 -- -- -- 400 -- -- -- -- 1.3 0.6 0.6 1.3 1.3 20 + 0.1 x Cb 20 + 0.1 x Cb 100 0.0 0.6 -- 0 50 100 400 -- -- -- -- -- 300 300 -- 0.9 -- 400 ns ns ns kHz s s s s s ns ns ns s s pF Max Fast-Mode Unit Max No. Characteristics Symbol/ Expression Min MOTOROLA DSP56364 Advance Information 2-53 Specifications Serial Host Interface (SHI) I2C Protocol Timing Table 2-18. SHI I2C Protocol Timing (Continued) Standard I2C* StandardMode Min HREQ in deassertion to last 184 SCL edge (HREQ in set-up time) First SCL sampling edge to HREQ output deassertion2 186 Filters bypassed Narrow filters enabled Wide filters enabled Last SCL edge to HREQ output not deasserted2 187 Filters bypassed Narrow filters enabled Wide filters enabled HREQ in assertion to first SCL edge 188 TAS;RQI 0.5 x TI2CCP Narrow filters enabled 0.5 x TC - 21 Filters bypassed Wide filters enabled Note: RP (min) = 1.5 k3/4 Fast-Mode No. Characteristics Symbol/ Expression Unit Max Max Min tSU;RQI 0.0 -- 0.0 -- ns TNG;RQO 2 x TC + 30 2 x TC + 120 2 x TC + 208 TAS;RQO 2 x TC + 30 2 x TC + 80 2 x TC + 135 50 100 155 -- -- -- 50 100 155 -- -- -- ns -- -- -- 50 140 228 -- -- -- 50 140 228 ns 4327 4282 4238 -- -- -- 927 882 838 -- -- -- ns 2-54 DSP56364 Advance Information MOTOROLA Specifications Serial Host Interface (SHI) I 2C Protocol Timing Programming the Serial Clock The programmed serial clock cycle, T I2CCP , is specified by the value of the HDM[5:0] and HRS bits of the HCKR (SHI clock control register). The expression for T I2CCP is T I2CCP = [TC x 2 x (HDM[7:0] + 1) x (7 x (1 - HRS) + 1)] where - - - HRS is the prescaler rate select bit. When HRS is cleared, the fixed divide-by-eight prescaler is operational. When HRS is set, the prescaler is bypassed. HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 64 (HDM[5:0] = 0 to $3F) may be selected. In I2C mode, the user may select a value for the programmed serial clock cycle from 6 x TC to 4096 x TC (if HDM[7:0] = $FF and HRS = 0) (if HDM[5:0] = $02 and HRS = 1) The programmed serial clock cycle (TI2CCP ), SCL rise time (TR), and the filters selected should be chosen in order to achieve the desired SCL frequency, as shown in Table 2-23. Table 2-19. SCL Serial Clock Cycle generated as Master Filters bypassed TI2CCP + 2.5 x TC + 45ns + TR Narrow filters enabled TI2CCP + 2.5 x TC + 135ns + TR Wide filters enabled TI2CCP + 2.5 x TC + 223ns + TR EXAMPLE: For DSP clock frequency of 100 MHz (i.e. TC = 10ns), operating in a standard-mode I2C environment (FSCL = 100 KHz (i.e. TSCL = 10s), TR = 1000ns), with filters bypassed TI2CCP = 10s - 2.5x10ns - 45ns - 1000ns = 8930ns MOTOROLA DSP56364 Advance Information 2-55 Specifications Serial Host Interface (SHI) I2C Protocol Timing Choosing HRS = 0 gives HDM[7:0] = 8930ns / (2x 10nsx 8) - 1 = 55.8 Thus the HDM[7:0] value should be programmed to $38 (=56). 171 173 SCL 177 172 179 SDA Stop Start MSB LSB ACK Stop 176 175 178 180 174 189 188 HREQ 186 184 182 183 187 AA0275 Figure 2-22. I2C Timing 2-56 DSP56364 Advance Information MOTOROLA Specifications Enhanced Serial Audio Interface Timing ENHANCED SERIAL AUDIO INTERFACE TIMING Table 2-20. Enhanced Serial Audio Interface Timing No. Characteristics1, 2, 3 Symbol Expression 4 x TC 430 Clock cycle5 tSSICC 3 x TC TXC:max[3*tc; t454] Clock high period * For internal clock 431 * For external clock Clock low period * For internal clock 432 * For external clock 433 RXC rising edge to FSR out (bl) high 434 RXC rising edge to FSR out (bl) low 435 RXC rising edge to FSR out (wr) high6 436 RXC rising edge to FSR out (wr) low6 437 RXC rising edge to FSR out (wl) high 438 RXC rising edge to FSR out (wl) low 439 Data in setup time before RXC (SCK in synchronous mode) falling edge -- -- -- -- -- -- -- -- -- -- -- -- 2 x TC - 10.0 1.5 x TC 2 x TC - 10.0 1.5 x TC -- -- -- -- -- -- -- -- -- -- Min 40.0 30.0 40.0 10.0 15.0 10.0 15.0 -- -- -- -- -- -- -- -- -- -- -- -- 0.0 19.0 5.0 3.0 23.0 1.0 1.0 23.0 Max -- -- -- -- ns -- -- ns -- 37.0 22.0 37.0 22.0 39.0 24.0 39.0 24.0 36.0 21.0 37.0 22.0 -- -- -- -- -- -- -- -- x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck x ck i ck x ck i ck a x ck i ck a ns ns ns ns ns ns ns ns ns ns CondUnit ition4 i ck x ck x ck ns 440 Data in hold time after RXC falling edge 441 442 FSR input (bl, wr) high before RXC falling edge 6 FSR input (wl) high before RXC falling edge MOTOROLA DSP56364 Advance Information 2-57 Specifications Enhanced Serial Audio Interface Timing Table 2-20. Enhanced Serial Audio Interface Timing (Continued) No. Characteristics1, 2, 3 FSR input hold time after RXC falling edge Flags input setup before RXC falling edge Flags input hold time after RXC falling edge Symbol Expression Min 3.0 0.0 0.0 19.0 6.0 0.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2.0 21.0 -- Max -- -- -- -- -- -- 29.0 15.0 31.0 17.0 31.0 17.0 33.0 19.0 30.0 16.0 31.0 17.0 31.0 17.0 34.0 20.0 28.0 21.0 31.0 16.0 34.0 20.0 -- -- 27.0 CondUnit ition4 x ck i ck a x ck i ck s x ck i ck s x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 443 444 445 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 23 + 0.5 x TC 21.0 -- -- -- -- 446 TXC rising edge to FST out (bl) high 447 TXC rising edge to FST out (bl) low 448 TXC rising edge to FST out (wr) high6 449 TXC rising edge to FST out (wr) low6 450 TXC rising edge to FST out (wl) high 451 TXC rising edge to FST out (wl) low 452 453 TXC rising edge to data out enable from high impedance TXC rising edge to transmitter #0 drive enable assertion 454 TXC rising edge to data out valid 455 456 457 458 TXC rising edge to data out high impedance7 TXC rising edge to transmitter #0 drive enable deassertion7 FST input (bl, wr) setup time before TXC falling edge6 FST input (wl) to data out enable from high impedance 2-58 DSP56364 Advance Information MOTOROLA Specifications Enhanced Serial Audio Interface Timing Table 2-20. Enhanced Serial Audio Interface Timing (Continued) No. Characteristics1, 2, 3 FST input (wl) to transmitter #0 drive enable assertion FST input (wl) setup time before TXC falling edge FST input hold time after TXC falling edge Symbol Expression Min Max CondUnit ition4 -- x ck i ck x ck i ck x ck i ck ns ns ns ns ns ns ns 459 460 461 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2.0 21.0 4.0 0.0 -- -- 40.0 -- -- 31.0 -- -- -- -- 32.0 18.0 -- 27.5 27.5 462 Flag output valid after TXC rising edge 463 HCKR/HCKT clock cycle 464 HCKT input rising edge to TXC output 465 HCKR input rising edge to RXC output Notes: 1. 2. 3. 4. 5. 6. 7. VCC = 3.16 V 0.16 V; TJ = 0C to +105C, CL = 50 pF i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that TXC and RXC are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies that TXC and RXC are the same clock) bl = bit length wl = word length wr = word length relative TXC(SCKT pin) = transmit clock RXC(SCKR pin) = receive clock FST(FST pin) = transmit frame sync FSR(FSR pin) = receive frame sync HCKT(HCKT pin) = transmit high speed clock HCKR(HCKR pin) = receive high speed clock For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit clock of the first word in frame. Periodically sampled and not 100% tested MOTOROLA DSP56364 Advance Information 2-59 Specifications Enhanced Serial Audio Interface Timing 430 TXC (Input/ Output) 431 432 446 FST (Bit) Out 447 450 451 FST (Word) Out 454 452 454 455 First Bit Last Bit Data Out 459 Transmitter #0 Drive Enable 457 461 453 456 FST (Bit) In 458 460 FST (Word) In 461 462 See Note Flags Out Note: In network mode, output flag transitions can occur at the start of each time slot within the frame. In normal mode, the output flag state is asserted for the entire frame period. AA0490 Figure 2-23. ESAI Transmitter Timing 2-60 DSP56364 Advance Information MOTOROLA Specifications Enhanced Serial Audio Interface Timing 430 431 RXC (Input/Output) 433 FSR (Bit) Out 437 FSR (Word) Out 440 439 Data In 441 FSR (Bit) In 442 FSR (Word) In 444 Flags In AA0491 432 434 438 First Bit 443 Last Bit 443 445 Figure 2-24. ESAI Receiver Timing MOTOROLA DSP56364 Advance Information 2-61 Specifications Enhanced Serial Audio Interface Timing HCKT SCKT(output) 463 464 Figure 2-25. ESAI HCKT Timing HCKR SCKR (output) 463 465 Figure 2-26. ESAI HCKR Timing 2-62 DSP56364 Advance Information MOTOROLA Specifications GPIO Timing GPIO TIMING Table 2-21. GPIO Timing No. Characteristics1 Expression Min -- 4.8 10.2 1.8 6.75 x TC-1.8 65.7 -- -- -- -- Max Unit 32.8 -- -- -- -- 13 13 ns ns ns ns ns ns ns 4902 EXTAL edge to GPIO out valid (GPIO out delay time) 491 EXTAL edge to GPIO out not valid (GPIO out hold time) 492 GPIO In valid to EXTAL edge (GPIO in set-up time) 493 EXTAL edge to GPIO in not valid (GPIO in hold time) 4942 Fetch to EXTAL edge before GPIO change 495 GPIO out rise time 496 GPIO out fall time Notes: 1. 2. VCC = 3.3 V 0.16 V; TJ = 0C to +105C, CL = 50 pF Valid only when PLL enabled with multiplication factor equal to one. EXTAL (Input) 490 491 GPIO (Output) 492 GPIO (Input) Valid 493 A0-A17 494 Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO and R0 contains the address of GPIO data register. GPIO (Output) 495 496 Figure 2-27. GPIO Timing MOTOROLA DSP56364 Advance Information 2-63 Specifications JTAG Timing JTAG TIMING Table 2-22. JTAG Timing All frequencies No. Characteristics Min 500 TCK frequency of operation (1/(TC x 3); maximum 22 MHz) 501 TCK cycle time in Crystal mode 502 TCK clock pulse width measured at 1.5 V 503 TCK rise and fall times 504 Boundary scan input data setup time 505 Boundary scan input data hold time 506 TCK low to output data valid 507 TCK low to output high impedance 508 TMS, TDI data setup time 509 TMS, TDI data hold time 510 TCK low to TDO data valid 511 TCK low to TDO high impedance Notes: 1. 2. Unit Max 22.0 -- -- 3.0 -- -- 40.0 40.0 -- -- 44.0 44.0 MHz ns ns ns ns ns ns ns ns ns ns ns 0.0 45.0 20.0 0.0 5.0 24.0 0.0 0.0 5.0 25.0 0.0 0.0 VCC = 3.3 V 0.16 V; TJ = 0C to +105C, CL = 50 pF All timings apply to OnCE module data transfers because it uses the JTAG port as an interface. 501 502 TCK (Input) VIH VM VIL 502 VM 503 503 AA0496 Figure 2-28. Test Clock Input Timing Diagram 2-64 DSP56364 Advance Information MOTOROLA Specifications JTAG Timing TCK (Input) VIL 504 VIH 505 Data Inputs 506 Data Outputs 507 Data Outputs 506 Data Outputs Input Data Valid Output Data Valid Output Data Valid AA0497 Figure 2-29. Boundary Scan (JTAG) Timing Diagram TCK (Input) TDI TMS (Input) VIH VIL 508 509 Input Data Valid 510 TDO (Output) 511 TDO (Output) 510 TDO (Output) Output Data Valid Output Data Valid AA0498 Figure 2-30. Test Access Port Timing Diagram MOTOROLA DSP56364 Advance Information 2-65 Specifications JTAG Timing 2-66 DSP56364 Advance Information MOTOROLA SECTION 3 PACKAGING PIN-OUT AND PACKAGE INFORMATION This section provides information about the available package for this product, including diagrams of the package pinouts and tables describing how the signals described in Section 1 are allocated for the package. The DSP56364 is available in a 100-pin TQFP package. Tables 31 and 3-2 show the pin/name assignments for the packages. TQFP Package Description Top view of the 100-pin TQFP package is shown in Figure 3-1 with its pin-outs. The 100-pin TQFP package mechanical drawing is shown in Figure 3-2. MOTOROLA DSP56364 Advance Information 3-1 Packaging Pin-out and Package Information VCCHQ VCCLQ GPIO3 GPIO2 GPIO1 GPIO0 GNDQ GNDD GNDS VCCD VCCS TDO TMS TCK TDI NC NC NC D7 D6 D5 D4 D3 78 D2 77 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 MODD MODB MODA FST FSR SCKT SCKR VCCS GNDS HCKT VCCLQ GNDQ HCKR SDO0 VCCHQ SDO1 SDO2/SDI3 SDO3/SDI2 SDO4/SDI1 SDO5/SDI0 VCCS GNDS SS/HA2 MOSI/HA0 MISO/SDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 D1 D0 A17 A16 GNDA VCCA A15 A14 A13 A12 VCCLQ GNDQ GNDA VCCA A11 VCCQH A10 A9 A8 A7 GNDA VCCA A6 A5 A4 A3 DSP56364 100-Pin TQPF PINIT/NMI PCAP VCCP CAS TA VCCQL GNDP EXTAL VCCA AA1 AA0 A0 A1 WR SCK/SCL RESET VCCHQ Figure 3-1 DSP56364 100-Pin Thin Quad Flat Pack (TQFP), Top View 3-2 DSP56364 Advance Information GNDQ GNDC GNDA NC RD HREQ VCCC A2 MOTOROLA Packaging Pin-out and Package Information Table 3-1 DSP56364 100-Pin TQFP Signal Identification by Pin Number Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Note: Signal Name MODD/IRQD MODB/IRQB MODA/IRQA FST FSR SCKT SCKR VCCS GNDS HCKT VCCLQ GNDQ HCKR SDO0 VCCHQ SDO1 SDO2/SDI3 SDO3/SDI2 SDO4/SDI1 SDO5/SDI0 VCCS GNDS SS/HA2 MOSI/HA0 MISO/SDA Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Signal Name SCK/SCL HREQ PINIT/NMI RESET No Connect VCCP PCAP GNDP EXTAL VCCHQ GNDQ VCCLQ TA CAS WR RD VCCC GNDC AA1/RAS1 AA0/RAS0 A0 A1 VCCQ GNDQ A2 Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 A3 A4 A5 A6 VCCA GNDA A7 A8 A9 A10 VCCHQ A11 VCCA GNDA GNDQ VCCLQ A12 A13 A14 A15 VCCA GNDA A16 A17 D0 Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 D1 D2 D3 Signal Name VCCD GNDD D4 D5 D6 D7 No Connect No Connect VCCLQ GNDQ VCCHQ No Connect GPIO0 VCCS GNDS GPIO1 GPIO2 GPIO3 TDO TDI TCK TMS Signal names are based on configured functionality. Most pins supply a single signal. Some pins provide a signal with dual functionality, such as the MODx/IRQx pins that select an operating mode after RESET is deasserted, but act as interrupt lines during operation. MOTOROLA DSP56364 Advance Information 3-3 Packaging Pin-out and Package Information Table 3-2 DSP56364 100-Pin TQFP Signal Identification by Name Signal Name A0 A1 A10 A11 A12 A13 A14 A15 A16 A17 A2 A3 A4 A5 A6 A7 A8 A9 AA0 AA1 CAS D0 D1 D2 D3 Pin No. 46 47 60 62 67 68 69 70 73 74 50 51 52 53 54 57 58 59 45 44 39 75 76 77 78 Signal Name D4 D5 D6 D7 EXTAL FSR FST GNDA GNDA GNDA GNDA GNDC GNDD GNDP GNDQ GNDQ GNDQ GNDQ GNDS GNDS GNDS GPIO0 GPIO1 GPIO2 GPIO3 Pin No. 81 82 83 84 34 5 4 49 56 64 72 43 80 33 12 36 65 88 9 22 93 91 94 95 96 Signal Name HCKR HCKT HREQ MISO/SDA MODA/IRQA MODB/IRQB MODD/IRQD MOSI/HA0 No Connect No Connect No Connect No Connect PCAP PINIT/NMI RD RESET SCK/SCL SCKR SCKT SDO0 SDO1 SDO5/SDI0 SS/HA2 SDO2/SDI3 SDO3/SDI2 Pin No. 13 10 27 25 3 2 1 24 30 85 86 90 32 28 41 29 26 7 6 14 16 20 23 17 18 Signal Name SDO4/SDI1 TA TCK TDI TD0 TMS VCCA VCCA VCCA VCCA VCCC VCCD VCCHQ VCCHQ VCCHQ VCCHQ VCCLQ VCCLQ VCCLQ VCCLQ VCCP VCCS VCCS VCCS WR Pin No. 19 38 99 98 97 100 48 55 63 71 42 79 15 35 61 89 11 37 66 87 31 8 21 92 40 3-4 DSP56364 Advance Information MOTOROLA Packaging Pin-out and Package Information TQFP Package Mechanical Drawing Figure 3-2 DSP56364 100-pin TQFP Package MOTOROLA DSP56364 Advance Information 3-5 Packaging Ordering Drawings ORDERING DRAWINGS The detailed package drawing is available on the Motorola web page at: http://mot.sps.com/cgi-bin/cases Use package 983 for the search. 3-6 DSP56364 Advance Information MOTOROLA Packaging Ordering Drawings MOTOROLA DSP56364 Advance Information 3-7 Packaging Ordering Drawings 3-8 DSP56364 Advance Information MOTOROLA Packaging Ordering Drawings 4X PIN 1 IDENT 1 112 0.20 T LM N 4X 28 TIPS 85 84 0.20 T LM N J1 J1 C L 4X P VIEW Y 108X G X X=L, M OR N VIEW Y B L M B1 V1 V J AA 28 57 F D 0.13 M BASE METAL 29 56 T LM N N A1 S1 A S SECTION J1J1 ROTATED 90 COUNTERCLOCKWISE C2 C 0.050 2 VIEW AB 0.10 T 112X SEATING PLANE 3 T NOTES: 1. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M AND N TO BE DETERMINED AT SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B INCLUDE MOLD MISMATCH. 6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.46. DIM A A1 B B1 C C1 C2 D E F G J K P R1 R2 S S1 V V1 Y Z AA 1 2 3 MILLIMETERS MAX MIN 20.000 BSC 10.000 BSC 20.000 BSC 10.000 BSC 1.600 0.050 0.150 1.350 1.450 0.270 0.370 0.450 0.750 0.270 0.330 0.650 BSC 0.090 0.170 0.500 REF 0.325 BSC 0.100 0.200 0.100 0.200 22.000 BSC 11.000 BSC 22.000 BSC 11.000 BSC 0.250 REF 1.000 REF 0.090 0.160 0 8 3 7 11 13 11 13 R R2 0.25 GAGE PLANE R R1 C1 (Y) (Z) VIEW AB (K) E 1 CASE 98701 ISSUE A DATE 01/30/96 MOTOROLA DSP56364 Advance Information 3-9 Packaging Ordering Drawings 3-10 DSP56364 Advance Information MOTOROLA SECTION 4 DESIGN CONSIDERATIONS THERMAL DESIGN CONSIDERATIONS An estimation of the chip junction temperature, TJ, in C can be obtained from the following equation: T J = TA + ( P D x R JA ) Where: TA = ambient temperature C RqJA = package junction-to-ambient thermal resistance C/W PD = power dissipation in package W Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance. R JA = R JC + RCA Where: RJA = package junction-to-ambient thermal resistance C/W RJC = package junction-to-case thermal resistance C/W RCA = package case-to-ambient thermal resistance C/W RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on a PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from RJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. MOTOROLA DSP56364 Advance Information 4-1 Design Considerations Thermal Design Considerations A complicating factor is the existence of three common ways for determining the junction-tocase thermal resistance in plastic packages. * To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. If the temperature of the package case (TT) is determined by a thermocouple, the thermal resistance is computed using the value obtained by the equation (TJ - TT)/PD. * * As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual temperature. Hence, the new thermal metric, thermal characterization parameter or JT, has been defined to be (TJ - TT)/ PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. 4-2 DSP56364 Advance Information MOTOROLA Design Considerations Electrical Design Considerations ELECTRICAL DESIGN CONSIDERATIONS CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC). The suggested value for a pullup or pulldown resistor is 10 k ohm. Use the following list of recommendations to assure correct DSP operation: * * * * * Provide a low-impedance path from the board power supply to each VCC pin on the DSP and from the board ground to each GND pin. Use at least six 0.01-0.1 F bypass capacitors positioned as close as possible to the four sides of the package to connect the VCC power source to GND. Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and GND pins are less than 1.2 cm (0.5 inch) per capacitor lead. Use at least a four-layer PCB with two inner layers for VCC and GND. Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This recommendation particularly applies to the address and data buses as well as the IRQA, IRQB, IRQD, and TA pins. Maximum PCB trace lengths on the order of 15 cm (6 inches) are recommended. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VCC and GND circuits. All inputs must be terminated (i.e., not allowed to float) using CMOS levels, except for the three pins with internal pull-up resistors (TMS, TDI, TCK). Take special care to minimize noise levels on the V CCP and GNDP pins. If multiple DSP56364 devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices. RESET must be asserted when the chip is powered up. A stable EXTAL signal must be supplied before deassertion of RESET. * * * * * MOTOROLA DSP56364 Advance Information 4-3 Design Considerations Power Consumption Considerations * At power-up, ensure that the voltage difference between the 5 V tolerant pins and the chip VCC never exceeds 3.95 V. POWER CONSUMPTION CONSIDERATIONS Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current consumption are described in this section. Most of the current consumed by CMOS devices is alternating current (ac), which is charging and discharging the capacitances of the pins and internal nodes. Current consumption is described by the following formula: I = CxVxf where C = node/pin capacitance V = voltage swing f = frequency of node/pin toggle Example 1 Current Consumption For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, and with a 100 MHz clock, toggling at its maximum possible rate (50 MHz), the current consumption is I = 50 x 10 - 12 x 3.3 x 50 x 10 = 8.25mA 6 The maximum internal current (ICCImax) value reflects the typical possible switching of the internal buses on best-case operation conditions, which is not necessarily a real application case. The typical internal current (ICCItyp) value reflects the average switching of the internal buses on typical operating conditions. For applications that require very low current consumption, do the following: * * * * * * Set the EBD bit when not accessing external memory. Minimize external memory accesses and use internal memory accesses. Minimize the number of pins that are switching. Minimize the capacitive load on the pins. Connect the unused inputs to pull-up or pull-down resistors. Disable unused peripherals. 4-4 DSP56364 Advance Information MOTOROLA Design Considerations PLL Performance Issues One way to evaluate power consumption is to use a current per MIPS measurement methodology to minimize specific board effects (i.e., to compensate for measured board current not caused by the DSP). A benchmark power consumption test algorithm is listed in Appendix A. Use the test algorithm, specific test current measurements, and the following equation to derive the current per MIPS value. I MIPS = I MHz = ( I typF2 - I typF1 ) ( F2 - F1 ) where : ItypF2 ItypF1 F2 F1 = = = = current at F2 current at F1 high frequency (any specified operating frequency) low frequency (any specified operating frequency lower than F2) Note: F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33 MHz. The degree of difference between F1 and F2 determines the amount of precision with which the current rating can be determined for an application. PLL PERFORMANCE ISSUES The following explanations should be considered as general observations on expected PLL behavior. There is no testing that verifies these exact numbers. These observations were measured on a limited number of parts and were not verified over the entire temperature and voltage ranges. Input (EXTAL) Jitter Requirements The allowed jitter on the frequency of EXTAL is 0.5%. If the rate of change of the frequency of EXTAL is slow (i.e., it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a long time), then the allowed jitter can be 2%. The phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed values. MOTOROLA DSP56364 Advance Information 4-5 Design Considerations PLL Performance Issues 4-6 DSP56364 Advance Information MOTOROLA SECTION 5 ORDERING INFORMATION Consult a Motorola Semiconductor sales office or authorized distributor to determine product availability and to place an order. Table 5-1 Ordering Information Part DSP56364 Notes: 1. Supply Voltage 3.3 V Package Type Thin quad flat pack (TQFP) Quad flat pack (QFP) Pin Count 100 112 Frequency (MHz) 100 100 Order Number XCB56364FU100 XCB56364PV100 2. The DSP56364 can include factory-programmed ROM. The listed `B' ROM code is a generic unused ROM available to any customer. Variations will be supported for Dolby digital (AC-3), DTS, MPEG2, and other features. These products are only available to authorized licensees of those technologies. Please consult the web site at www.dspaudio.motorola.com for current availability. Future products in the DSP56364 family may include other ROM-based options. For additional information on future part development, or to request customer-specific ROMbased support, call your local Motorola Semiconductor sales office or authorized distributor. MOTOROLA DSP56364 Advance Information 5-1 Ordering Information 5-2 DSP56364 Advance Information MOTOROLA APPENDIX A IBIS MODEL [IBIS ver] 2.1 [File name] 56364.ibs [File Rev] 0.0 [Date] 29/6/2000 [Component] 56364 [Manufacturer] Motorola [Package] |variable typ R_pkg 45m L_pkg 2.5nH C_pkg 1.3pF min 22m 1.1nH 1.2pF max 75m 4.3nH 1.4pF [Pin]signal_name model_name 1 irqc_ ip5b_i 2 irqb_ ip5b_i 3 irqa_ ip5b_i 4 fst ip5b_io 5 fsr ip5b_io 6 sckt ip5b_io 7 sckr ip5b_io 8 svcc power 9 sgnd gnd 10 hsckt ip5b_io 11 qvccl power 12 qgnd gnd 13 hsckr ip5b_io 14 sdo0 ip5b_io 15 qvcch power 16 sdo1 ip5b_io 17 sdo2 ip5b_io 18 sdo3 ip5b_io 19 sdo4 ip5b_io 20 sdo5 ip5b_io 21 svcc power 22 sgnd gnd 23 ss_ ip5b_io 24 mosi ip5b_io 25 sda ip5b_io 26 sck ip5b_io 27 hreq_ ip5b_io 28 nmi_ ip5b_i 29 ires_ ip5b_i 31 pvcc power 32 pcap power MOTOROLA DSP56364 Advance Information Appendix A-1 IBIS Model 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 87 pgnd cxtldis_ qvcch qgnd qvccl ta_ cas_ wr_ rd_ cvcc cgnd aa1 aa0 eab0 eab1 avcc agnd eab2 eab3 eab4 eab5 eab6 avcc agnd eab7 eab8 eab9 eab10 qvcch eab11 avcc agnd qgnd qvccl eab12 eab13 eab14 eab15 avcc agnd eab16 eab17 edb0 edb1 edb2 edb3 dvcc dgnd edb4 edb5 edb6 edb7 qvccl gnd iexlh_i power gnd power icbc_o icbc_o icbc_o icbc_o power gnd icbc_o icbc_o icba_o icba_o power gnd icba_o icba_o icba_o icba_o icba_o power gnd icba_o icba_o icba_o icba_o power icba_o power gnd gnd power icba_o icba_o icba_o icba_o power gnd icba_o icba_o icba_io icba_io icba_io icba_io power gnd icba_io icba_io icba_io icba_io power Appendix A-2 DSP56364 Advance Information MOTOROLA IBIS Model 88 qgnd gnd 89 qvcch power 91 edb8 ip5b_io 92 svcc power 93 sgnd gnd 94 edb9 ip5b_io 95 edb10 ip5b_io 96 edb11 ip5b_io 97 tdo ip5b_o 98 tdi ip5b_i 99 tck ip5b_i 100 tms ip5b_i | [Model] ip5b_i Model_type Input Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [GND_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -9.69e-03 -1.18e+00 -7.81e-03 -7.00e-01 -2.83e-04 -5.70e-03 -8.42e-04 -5.00e-01 -1.35e-06 -4.53e-05 -1.00e-05 -3.00e-01 -1.31e-09 -3.74e-07 -8.58e-09 -1.00e-01 -2.92e-11 -3.00e-09 -3.64e-11 0.000e+00 -2.44e-11 -5.14e-10 -2.79e-11 | [End]| [Model] ip5b_io Model_type I/O Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF | | MOTOROLA DSP56364 Advance Information Appendix A-3 IBIS Model [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.69e+00 -9.00e-01 -5.10e-02 -1.18e+00 -5.63e-02 -7.00e-01 -3.65e-02 -2.25e-02 -4.28e-02 -5.00e-01 -2.65e-02 -1.38e-02 -3.12e-02 -3.00e-01 -1.62e-02 -8.35e-03 -1.91e-02 -1.00e-01 -5.49e-03 -2.80e-03 -6.52e-03 1.000e-01 5.377e-03 2.744e-03 6.427e-03 3.000e-01 1.516e-02 7.871e-03 1.823e-02 5.000e-01 2.370e-02 1.252e-02 2.869e-02 7.000e-01 3.098e-02 1.667e-02 3.776e-02 9.000e-01 3.700e-02 2.026e-02 4.544e-02 1.100e+00 4.175e-02 2.324e-02 5.171e-02 1.300e+00 4.531e-02 2.553e-02 5.660e-02 1.500e+00 4.779e-02 2.709e-02 6.023e-02 1.700e+00 4.935e-02 2.803e-02 6.271e-02 1.900e+00 5.013e-02 2.851e-02 6.419e-02 2.100e+00 5.046e-02 2.876e-02 6.494e-02 2.300e+00 5.063e-02 2.892e-02 6.525e-02 2.500e+00 5.075e-02 2.904e-02 6.540e-02 2.700e+00 5.085e-02 2.912e-02 6.549e-02 2.900e+00 5.090e-02 2.876e-02 6.555e-02 3.100e+00 4.771e-02 2.994e-02 6.561e-02 3.300e+00 4.525e-02 3.321e-02 6.182e-02 3.500e+00 4.657e-02 3.570e-02 6.049e-02 3.700e+00 4.904e-02 3.801e-02 6.178e-02 3.900e+00 5.221e-02 4.029e-02 6.450e-02 4.100e+00 5.524e-02 4.253e-02 6.659e-02 4.300e+00 5.634e-02 4.463e-02 6.867e-02 4.500e+00 5.751e-02 4.645e-02 6.970e-02 4.700e+00 5.634e-02 4.786e-02 6.938e-02 4.900e+00 5.648e-02 4.881e-02 6.960e-02 5.100e+00 5.664e-02 4.912e-02 6.983e-02 5.300e+00 5.679e-02 4.795e-02 7.005e-02 5.500e+00 5.693e-02 4.679e-02 7.026e-02 5.700e+00 5.707e-02 4.688e-02 7.049e-02 5.900e+00 5.722e-02 4.700e-02 7.074e-02 6.100e+00 5.741e-02 4.712e-02 7.105e-02 6.300e+00 5.766e-02 4.723e-02 7.147e-02 Appendix A-4 DSP56364 Advance Information MOTOROLA IBIS Model 6.500e+00 6.600e+00 | [Pullup] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 5.801e-02 5.824e-02 4.733e-02 4.737e-02 7.205e-02 7.242e-02 I(typ) 2.922e-04 2.881e-04 2.853e-04 2.836e-04 2.825e-04 2.819e-04 2.815e-04 2.813e-04 2.812e-04 2.811e-04 2.810e-04 2.809e-04 2.808e-04 2.997e-04 1.750e-02 1.048e-02 3.487e-03 -3.40e-03 -9.69e-03 -1.52e-02 -2.02e-02 -2.46e-02 -2.84e-02 -3.14e-02 -3.37e-02 -3.55e-02 -3.68e-02 -3.78e-02 -3.85e-02 -3.91e-02 -3.96e-02 -4.01e-02 -4.04e-02 -4.08e-02 -4.11e-02 -4.14e-02 -4.17e-02 -4.32e-02 -4.08e-01 -2.73e+01 -6.13e+01 -9.54e+01 -1.38e+02 -1.89e+02 -2.40e+02 -2.91e+02 -3.42e+02 I(min) 2.177e-04 2.175e-04 2.173e-04 2.172e-04 2.171e-04 2.170e-04 2.169e-04 2.167e-04 2.520e-04 3.078e-02 2.684e-02 2.277e-02 1.864e-02 1.447e-02 1.031e-02 6.181e-03 2.084e-03 -2.03e-03 -5.71e-03 -8.99e-03 -1.19e-02 -1.43e-02 -1.62e-02 -1.77e-02 -1.88e-02 -1.95e-02 -2.00e-02 -2.04e-02 -2.07e-02 -2.10e-02 -2.12e-02 -2.15e-02 -2.17e-02 -2.18e-02 -2.20e-02 -2.78e-02 -1.20e+00 -2.15e+01 -4.52e+01 -6.89e+01 -9.25e+01 -1.17e+02 -1.52e+02 -1.88e+02 -2.23e+02 -2.59e+02 -2.94e+02 I(max) 4.123e-04 4.021e-04 3.946e-04 3.893e-04 3.857e-04 3.834e-04 3.820e-04 3.812e-04 3.808e-04 3.806e-04 3.804e-04 3.802e-04 3.801e-04 3.799e-04 3.797e-04 3.776e-04 4.568e-03 -4.22e-03 -1.24e-02 -1.95e-02 -2.61e-02 -3.21e-02 -3.73e-02 -4.18e-02 -4.55e-02 -4.85e-02 -5.09e-02 -5.27e-02 -5.41e-02 -5.51e-02 -5.60e-02 -5.67e-02 -5.74e-02 -5.79e-02 -5.84e-02 -5.89e-02 -5.94e-02 -5.98e-02 -6.10e-02 -6.84e-02 -7.73e+00 -4.18e+01 -7.59e+01 -1.11e+02 -1.61e+02 -2.12e+02 -2.63e+02 MOTOROLA DSP56364 Advance Information Appendix A-5 IBIS Model 6.100e+00 -3.93e+02 -3.30e+02 -3.14e+02 6.300e+00 -4.44e+02 -3.65e+02 -3.65e+02 6.500e+00 -4.95e+02 -4.01e+02 -4.16e+02 6.600e+00 -5.21e+02 -4.18e+02 -4.41e+02 | [GND_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -9.69e-03 -1.18e+00 -7.81e-03 -7.00e-01 -2.83e-04 -5.70e-03 -8.42e-04 -5.00e-01 -1.35e-06 -4.53e-05 -1.00e-05 -3.00e-01 -1.31e-09 -3.74e-07 -8.58e-09 -1.00e-01 -2.92e-11 -3.00e-09 -3.64e-11 0.000e+00 -2.44e-11 -5.14e-10 -2.79e-11 | [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) | | dV/dt_r 1.030/0.465 0.605/0.676 1.320/0.366 | | dV/dt_f 1.290/0.671 0.829/0.122 1.520/0.431 | [End]| [Model] ip5b_o Model_type 3-state Polarity Non-Inverting C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 Appendix A-6 DSP56364 Advance Information MOTOROLA IBIS Model -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [Pullup] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.65e+02 -2.14e+02 -1.63e+02 -1.13e+02 -7.83e+01 -4.43e+01 -1.02e+01 -5.10e-02 -3.65e-02 -2.65e-02 -1.62e-02 -5.49e-03 5.377e-03 1.516e-02 2.370e-02 3.098e-02 3.700e-02 4.175e-02 4.531e-02 4.779e-02 4.935e-02 5.013e-02 5.046e-02 5.063e-02 5.075e-02 5.085e-02 5.090e-02 4.771e-02 4.525e-02 4.657e-02 4.904e-02 5.221e-02 5.524e-02 5.634e-02 5.751e-02 5.634e-02 5.648e-02 5.664e-02 5.679e-02 5.693e-02 5.707e-02 5.722e-02 5.741e-02 5.766e-02 5.801e-02 5.824e-02 -1.88e+02 -1.52e+02 -1.17e+02 -9.25e+01 -6.88e+01 -4.52e+01 -2.15e+01 -1.18e+00 -2.25e-02 -1.38e-02 -8.35e-03 -2.80e-03 2.744e-03 7.871e-03 1.252e-02 1.667e-02 2.026e-02 2.324e-02 2.553e-02 2.709e-02 2.803e-02 2.851e-02 2.876e-02 2.892e-02 2.904e-02 2.912e-02 2.876e-02 2.994e-02 3.321e-02 3.570e-02 3.801e-02 4.029e-02 4.253e-02 4.463e-02 4.645e-02 4.786e-02 4.881e-02 4.912e-02 4.795e-02 4.679e-02 4.688e-02 4.700e-02 4.712e-02 4.723e-02 4.733e-02 4.737e-02 -2.63e+02 -2.12e+02 -1.61e+02 -1.10e+02 -7.58e+01 -4.17e+01 -7.69e+00 -5.63e-02 -4.28e-02 -3.12e-02 -1.91e-02 -6.52e-03 6.427e-03 1.823e-02 2.869e-02 3.776e-02 4.544e-02 5.171e-02 5.660e-02 6.023e-02 6.271e-02 6.419e-02 6.494e-02 6.525e-02 6.540e-02 6.549e-02 6.555e-02 6.561e-02 6.182e-02 6.049e-02 6.178e-02 6.450e-02 6.659e-02 6.867e-02 6.970e-02 6.938e-02 6.960e-02 6.983e-02 7.005e-02 7.026e-02 7.049e-02 7.074e-02 7.105e-02 7.147e-02 7.205e-02 7.242e-02 I(typ) 2.922e-04 2.881e-04 2.853e-04 I(min) 2.177e-04 2.175e-04 2.173e-04 I(max) 4.123e-04 4.021e-04 3.946e-04 MOTOROLA DSP56364 Advance Information Appendix A-7 IBIS Model -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [GND_clamp] |voltage | -3.30e+00 2.836e-04 2.825e-04 2.819e-04 2.815e-04 2.813e-04 2.812e-04 2.811e-04 2.810e-04 2.809e-04 2.808e-04 2.997e-04 1.750e-02 1.048e-02 3.487e-03 -3.40e-03 -9.69e-03 -1.52e-02 -2.02e-02 -2.46e-02 -2.84e-02 -3.14e-02 -3.37e-02 -3.55e-02 -3.68e-02 -3.78e-02 -3.85e-02 -3.91e-02 -3.96e-02 -4.01e-02 -4.04e-02 -4.08e-02 -4.11e-02 -4.14e-02 -4.17e-02 -4.32e-02 -4.08e-01 -2.73e+01 -6.13e+01 -9.54e+01 -1.38e+02 -1.89e+02 -2.40e+02 -2.91e+02 -3.42e+02 -3.93e+02 -4.44e+02 -4.95e+02 -5.21e+02 2.172e-04 2.171e-04 2.170e-04 2.169e-04 2.167e-04 2.520e-04 3.078e-02 2.684e-02 2.277e-02 1.864e-02 1.447e-02 1.031e-02 6.181e-03 2.084e-03 -2.03e-03 -5.71e-03 -8.99e-03 -1.19e-02 -1.43e-02 -1.62e-02 -1.77e-02 -1.88e-02 -1.95e-02 -2.00e-02 -2.04e-02 -2.07e-02 -2.10e-02 -2.12e-02 -2.15e-02 -2.17e-02 -2.18e-02 -2.20e-02 -2.78e-02 -1.20e+00 -2.15e+01 -4.52e+01 -6.89e+01 -9.25e+01 -1.17e+02 -1.52e+02 -1.88e+02 -2.23e+02 -2.59e+02 -2.94e+02 -3.30e+02 -3.65e+02 -4.01e+02 -4.18e+02 3.893e-04 3.857e-04 3.834e-04 3.820e-04 3.812e-04 3.808e-04 3.806e-04 3.804e-04 3.802e-04 3.801e-04 3.799e-04 3.797e-04 3.776e-04 4.568e-03 -4.22e-03 -1.24e-02 -1.95e-02 -2.61e-02 -3.21e-02 -3.73e-02 -4.18e-02 -4.55e-02 -4.85e-02 -5.09e-02 -5.27e-02 -5.41e-02 -5.51e-02 -5.60e-02 -5.67e-02 -5.74e-02 -5.79e-02 -5.84e-02 -5.89e-02 -5.94e-02 -5.98e-02 -6.10e-02 -6.84e-02 -7.73e+00 -4.18e+01 -7.59e+01 -1.11e+02 -1.61e+02 -2.12e+02 -2.63e+02 -3.14e+02 -3.65e+02 -4.16e+02 -4.41e+02 I(typ) -5.21e+02 I(min) -3.65e+02 I(max) -5.18e+02 Appendix A-8 DSP56364 Advance Information MOTOROLA IBIS Model -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -9.69e-03 -1.18e+00 -7.81e-03 -7.00e-01 -2.83e-04 -5.70e-03 -8.42e-04 -5.00e-01 -1.35e-06 -4.53e-05 -1.00e-05 -3.00e-01 -1.31e-09 -3.74e-07 -8.58e-09 -1.00e-01 -2.92e-11 -3.00e-09 -3.64e-11 0.000e+00 -2.44e-11 -5.14e-10 -2.79e-11 | [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) | | dV/dt_r 1.030/0.465 0.605/0.676 1.320/0.366 | | dV/dt_f 1.290/0.671 0.829/0.122 1.520/0.431 | [End]| [Model] icba_io Model_type I/O Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.68e+00 MOTOROLA DSP56364 Advance Information Appendix A-9 IBIS Model -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [Pullup] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -2.70e-02 -1.32e-02 -9.33e-03 -5.75e-03 -1.97e-03 1.945e-03 5.507e-03 8.649e-03 1.136e-02 1.364e-02 1.547e-02 1.688e-02 1.299e-01 1.366e-01 1.404e-01 1.423e-01 1.433e-01 1.440e-01 1.445e-01 1.450e-01 1.454e-01 1.458e-01 1.461e-01 1.464e-01 1.469e-01 1.490e-01 1.501e+00 1.813e+01 3.540e+01 5.269e+01 7.541e+01 1.012e+02 1.270e+02 1.527e+02 1.785e+02 2.043e+02 2.301e+02 2.559e+02 2.688e+02 -1.19e+00 -1.25e-02 -4.69e-03 -2.81e-03 -9.48e-04 9.285e-04 2.640e-03 4.168e-03 5.504e-03 6.636e-03 7.551e-03 8.240e-03 6.458e-02 6.746e-02 6.916e-02 7.006e-02 7.059e-02 7.098e-02 7.128e-02 7.154e-02 7.176e-02 7.196e-02 7.223e-02 8.810e-02 2.589e+00 1.451e+01 2.658e+01 3.866e+01 5.076e+01 6.461e+01 8.261e+01 1.006e+02 1.186e+02 1.366e+02 1.546e+02 1.726e+02 1.906e+02 2.086e+02 2.176e+02 -2.90e-02 -1.63e-02 -1.10e-02 -6.76e-03 -2.32e-03 2.307e-03 6.599e-03 1.048e-02 1.393e-02 1.693e-02 1.950e-02 2.162e-02 2.331e-02 1.755e-01 1.847e-01 1.907e-01 1.940e-01 1.958e-01 1.970e-01 1.979e-01 1.986e-01 1.993e-01 1.999e-01 2.004e-01 2.009e-01 2.015e-01 2.030e-01 2.385e-01 9.563e+00 2.682e+01 4.409e+01 6.258e+01 8.836e+01 1.141e+02 1.399e+02 1.657e+02 1.915e+02 2.173e+02 2.302e+02 I(typ) 2.686e+02 2.428e+02 2.170e+02 1.912e+02 1.655e+02 1.397e+02 1.139e+02 8.814e+01 6.237e+01 4.389e+01 I(min) 1.905e+02 1.725e+02 1.545e+02 1.365e+02 1.185e+02 1.005e+02 8.253e+01 6.454e+01 5.068e+01 3.859e+01 I(max) 2.686e+02 2.428e+02 2.170e+02 1.912e+02 1.655e+02 1.397e+02 1.139e+02 8.814e+01 6.237e+01 4.389e+01 Appendix A-10 DSP56364 Advance Information MOTOROLA IBIS Model -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [GND_clamp] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 2.662e+01 9.360e+00 4.275e-02 8.208e-03 5.635e-03 3.370e-03 1.118e-03 -1.09e-03 -3.12e-03 -4.96e-03 -6.60e-03 -8.04e-03 -9.26e-03 -1.03e-02 -1.25e-01 -1.31e-01 -1.36e-01 -1.40e-01 -1.42e-01 -1.44e-01 -1.46e-01 -1.48e-01 -1.49e-01 -1.50e-01 -1.52e-01 -1.53e-01 -1.54e-01 -1.57e-01 -5.25e-01 -2.74e+01 -6.14e+01 -9.55e+01 -1.38e+02 -1.89e+02 -2.40e+02 -2.91e+02 -3.42e+02 -3.93e+02 -4.44e+02 -4.95e+02 -5.21e+02 2.651e+01 1.444e+01 2.518e+00 2.012e-02 3.518e-03 2.053e-03 6.789e-04 -6.56e-04 -1.86e-03 -2.93e-03 -3.87e-03 -4.66e-03 -5.30e-03 -6.55e-02 -6.93e-02 -7.19e-02 -7.38e-02 -7.53e-02 -7.65e-02 -7.76e-02 -7.85e-02 -7.93e-02 -8.00e-02 -8.06e-02 -8.13e-02 -8.84e-02 -1.26e+00 -2.16e+01 -4.53e+01 -6.89e+01 -9.26e+01 -1.17e+02 -1.52e+02 -1.88e+02 -2.23e+02 -2.59e+02 -2.94e+02 -3.30e+02 -3.65e+02 -4.01e+02 -4.19e+02 2.662e+01 9.362e+00 4.663e-02 1.070e-02 7.068e-03 4.233e-03 1.410e-03 -1.38e-03 -3.99e-03 -6.39e-03 -8.59e-03 -1.06e-02 -1.23e-02 -1.38e-02 -1.70e-01 -1.82e-01 -1.91e-01 -1.97e-01 -2.03e-01 -2.07e-01 -2.10e-01 -2.13e-01 -2.15e-01 -2.17e-01 -2.19e-01 -2.21e-01 -2.22e-01 -2.24e-01 -2.27e-01 -2.38e-01 -7.90e+00 -4.20e+01 -7.60e+01 -1.11e+02 -1.61e+02 -2.12e+02 -2.63e+02 -3.14e+02 -3.65e+02 -4.16e+02 -4.42e+02 I(typ) -5.20e+02 -4.69e+02 -4.18e+02 -3.67e+02 -3.16e+02 -2.65e+02 -2.14e+02 -1.63e+02 I(min) -3.65e+02 -3.30e+02 -2.94e+02 -2.59e+02 -2.23e+02 -1.88e+02 -1.52e+02 -1.17e+02 I(max) -5.18e+02 -4.67e+02 -4.16e+02 -3.65e+02 -3.14e+02 -2.63e+02 -2.12e+02 -1.60e+02 MOTOROLA DSP56364 Advance Information Appendix A-11 IBIS Model -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -1.22e-02 -1.18e+00 -1.17e-02 -7.00e-01 -5.18e-04 -6.62e-03 -1.56e-03 -5.00e-01 -2.43e-06 -6.64e-05 -1.80e-05 -3.00e-01 -2.33e-09 -6.35e-07 -1.54e-08 -1.00e-01 -2.10e-11 -6.31e-09 -2.99e-11 0.000e+00 -1.70e-11 -1.95e-09 -1.91e-11 | [POWER_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 2.686e+02 1.905e+02 2.686e+02 -3.10e+00 2.428e+02 1.725e+02 2.428e+02 -2.90e+00 2.170e+02 1.545e+02 2.170e+02 -2.70e+00 1.912e+02 1.365e+02 1.912e+02 -2.50e+00 1.655e+02 1.185e+02 1.655e+02 -2.30e+00 1.397e+02 1.005e+02 1.397e+02 -2.10e+00 1.139e+02 8.253e+01 1.139e+02 -1.90e+00 8.814e+01 6.454e+01 8.814e+01 -1.70e+00 6.236e+01 5.068e+01 6.237e+01 -1.50e+00 4.389e+01 3.859e+01 4.389e+01 -1.30e+00 2.662e+01 2.651e+01 2.662e+01 -1.10e+00 9.358e+00 1.444e+01 9.359e+00 -9.00e-01 3.399e-02 2.517e+00 3.554e-02 -7.00e-01 3.426e-04 1.577e-02 9.211e-04 -5.00e-01 2.840e-06 7.857e-05 1.655e-05 -3.00e-01 3.401e-09 6.836e-07 1.946e-08 -1.00e-01 6.162e-11 7.379e-09 7.622e-11 0.000e+00 5.758e-11 2.438e-09 6.240e-11 | [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) | | dV/dt_r 1.680/0.164 1.360/0.329 1.900/0.124 | | dV/dt_f 1.690/0.219 1.310/0.442 1.880/0.155 | [End]| [Model] icba_o Model_type 3-state Polarity Non-Inverting C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) Appendix A-12 DSP56364 Advance Information MOTOROLA IBIS Model | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | -5.20e+02 -4.69e+02 -4.18e+02 -3.67e+02 -3.16e+02 -2.65e+02 -2.14e+02 -1.63e+02 -1.13e+02 -7.83e+01 -4.43e+01 -1.02e+01 -2.70e-02 -1.32e-02 -9.33e-03 -5.75e-03 -1.97e-03 1.945e-03 5.507e-03 8.649e-03 1.136e-02 1.364e-02 1.547e-02 1.688e-02 1.299e-01 1.366e-01 1.404e-01 1.423e-01 1.433e-01 1.440e-01 1.445e-01 1.450e-01 1.454e-01 1.458e-01 1.461e-01 1.464e-01 1.469e-01 1.490e-01 1.501e+00 1.813e+01 3.540e+01 5.269e+01 7.541e+01 1.012e+02 1.270e+02 1.527e+02 1.785e+02 2.043e+02 2.301e+02 2.559e+02 2.688e+02 -3.65e+02 -3.30e+02 -2.94e+02 -2.59e+02 -2.23e+02 -1.88e+02 -1.52e+02 -1.17e+02 -9.25e+01 -6.88e+01 -4.52e+01 -2.15e+01 -1.19e+00 -1.25e-02 -4.69e-03 -2.81e-03 -9.48e-04 9.285e-04 2.640e-03 4.168e-03 5.504e-03 6.636e-03 7.551e-03 8.240e-03 6.458e-02 6.746e-02 6.916e-02 7.006e-02 7.059e-02 7.098e-02 7.128e-02 7.154e-02 7.176e-02 7.196e-02 7.223e-02 8.810e-02 2.589e+00 1.451e+01 2.658e+01 3.866e+01 5.076e+01 6.461e+01 8.261e+01 1.006e+02 1.186e+02 1.366e+02 1.546e+02 1.726e+02 1.906e+02 2.086e+02 2.176e+02 -5.18e+02 -4.67e+02 -4.16e+02 -3.65e+02 -3.14e+02 -2.63e+02 -2.12e+02 -1.60e+02 -1.10e+02 -7.58e+01 -4.17e+01 -7.68e+00 -2.90e-02 -1.63e-02 -1.10e-02 -6.76e-03 -2.32e-03 2.307e-03 6.599e-03 1.048e-02 1.393e-02 1.693e-02 1.950e-02 2.162e-02 2.331e-02 1.755e-01 1.847e-01 1.907e-01 1.940e-01 1.958e-01 1.970e-01 1.979e-01 1.986e-01 1.993e-01 1.999e-01 2.004e-01 2.009e-01 2.015e-01 2.030e-01 2.385e-01 9.563e+00 2.682e+01 4.409e+01 6.258e+01 8.836e+01 1.141e+02 1.399e+02 1.657e+02 1.915e+02 2.173e+02 2.302e+02 MOTOROLA DSP56364 Advance Information Appendix A-13 IBIS Model [Pullup] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 I(typ) 2.686e+02 2.428e+02 2.170e+02 1.912e+02 1.655e+02 1.397e+02 1.139e+02 8.814e+01 6.237e+01 4.389e+01 2.662e+01 9.360e+00 4.275e-02 8.208e-03 5.635e-03 3.370e-03 1.118e-03 -1.09e-03 -3.12e-03 -4.96e-03 -6.60e-03 -8.04e-03 -9.26e-03 -1.03e-02 -1.25e-01 -1.31e-01 -1.36e-01 -1.40e-01 -1.42e-01 -1.44e-01 -1.46e-01 -1.48e-01 -1.49e-01 -1.50e-01 -1.52e-01 -1.53e-01 -1.54e-01 -1.57e-01 -5.25e-01 -2.74e+01 -6.14e+01 -9.55e+01 -1.38e+02 -1.89e+02 -2.40e+02 -2.91e+02 -3.42e+02 -3.93e+02 -4.44e+02 -4.95e+02 I(min) 1.905e+02 1.725e+02 1.545e+02 1.365e+02 1.185e+02 1.005e+02 8.253e+01 6.454e+01 5.068e+01 3.859e+01 2.651e+01 1.444e+01 2.518e+00 2.012e-02 3.518e-03 2.053e-03 6.789e-04 -6.56e-04 -1.86e-03 -2.93e-03 -3.87e-03 -4.66e-03 -5.30e-03 -6.55e-02 -6.93e-02 -7.19e-02 -7.38e-02 -7.53e-02 -7.65e-02 -7.76e-02 -7.85e-02 -7.93e-02 -8.00e-02 -8.06e-02 -8.13e-02 -8.84e-02 -1.26e+00 -2.16e+01 -4.53e+01 -6.89e+01 -9.26e+01 -1.17e+02 -1.52e+02 -1.88e+02 -2.23e+02 -2.59e+02 -2.94e+02 -3.30e+02 -3.65e+02 -4.01e+02 I(max) 2.686e+02 2.428e+02 2.170e+02 1.912e+02 1.655e+02 1.397e+02 1.139e+02 8.814e+01 6.237e+01 4.389e+01 2.662e+01 9.362e+00 4.663e-02 1.070e-02 7.068e-03 4.233e-03 1.410e-03 -1.38e-03 -3.99e-03 -6.39e-03 -8.59e-03 -1.06e-02 -1.23e-02 -1.38e-02 -1.70e-01 -1.82e-01 -1.91e-01 -1.97e-01 -2.03e-01 -2.07e-01 -2.10e-01 -2.13e-01 -2.15e-01 -2.17e-01 -2.19e-01 -2.21e-01 -2.22e-01 -2.24e-01 -2.27e-01 -2.38e-01 -7.90e+00 -4.20e+01 -7.60e+01 -1.11e+02 -1.61e+02 -2.12e+02 -2.63e+02 -3.14e+02 -3.65e+02 -4.16e+02 Appendix A-14 DSP56364 Advance Information MOTOROLA IBIS Model 6.600e+00 -5.21e+02 -4.19e+02 -4.42e+02 | [GND_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -1.22e-02 -1.18e+00 -1.17e-02 -7.00e-01 -5.18e-04 -6.62e-03 -1.56e-03 -5.00e-01 -2.43e-06 -6.64e-05 -1.80e-05 -3.00e-01 -2.33e-09 -6.35e-07 -1.54e-08 -1.00e-01 -2.10e-11 -6.31e-09 -2.99e-11 0.000e+00 -1.70e-11 -1.95e-09 -1.91e-11 | [POWER_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 2.686e+02 1.905e+02 2.686e+02 -3.10e+00 2.428e+02 1.725e+02 2.428e+02 -2.90e+00 2.170e+02 1.545e+02 2.170e+02 -2.70e+00 1.912e+02 1.365e+02 1.912e+02 -2.50e+00 1.655e+02 1.185e+02 1.655e+02 -2.30e+00 1.397e+02 1.005e+02 1.397e+02 -2.10e+00 1.139e+02 8.253e+01 1.139e+02 -1.90e+00 8.814e+01 6.454e+01 8.814e+01 -1.70e+00 6.236e+01 5.068e+01 6.237e+01 -1.50e+00 4.389e+01 3.859e+01 4.389e+01 -1.30e+00 2.662e+01 2.651e+01 2.662e+01 -1.10e+00 9.358e+00 1.444e+01 9.359e+00 -9.00e-01 3.399e-02 2.517e+00 3.554e-02 -7.00e-01 3.426e-04 1.577e-02 9.211e-04 -5.00e-01 2.840e-06 7.857e-05 1.655e-05 -3.00e-01 3.401e-09 6.836e-07 1.946e-08 -1.00e-01 6.162e-11 7.379e-09 7.622e-11 0.000e+00 5.758e-11 2.438e-09 6.240e-11 | [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) | | dV/dt_r 1.680/0.164 1.360/0.329 1.900/0.124 | MOTOROLA DSP56364 Advance Information Appendix A-15 IBIS Model | dV/dt_f 1.690/0.219 1.310/0.442 1.880/0.155 | [End]| [Model] icbc_o Model_type 3-state Polarity Non-Inverting C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.11e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.42e+01 -4.51e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -2.51e-02 -1.18e+00 -2.65e-02 -7.00e-01 -1.30e-02 -1.16e-02 -1.58e-02 -5.00e-01 -9.33e-03 -4.67e-03 -1.10e-02 -3.00e-01 -5.75e-03 -2.81e-03 -6.76e-03 -1.00e-01 -1.97e-03 -9.48e-04 -2.32e-03 1.000e-01 1.945e-03 9.285e-04 2.307e-03 3.000e-01 5.507e-03 2.640e-03 6.599e-03 5.000e-01 8.649e-03 4.168e-03 1.048e-02 7.000e-01 1.136e-02 5.504e-03 1.393e-02 9.000e-01 1.364e-02 6.636e-03 1.693e-02 1.100e+00 1.547e-02 7.551e-03 1.950e-02 1.300e+00 1.688e-02 8.240e-03 2.162e-02 1.500e+00 9.632e-02 4.783e-02 2.331e-02 1.700e+00 1.012e-01 4.994e-02 1.302e-01 1.900e+00 1.039e-01 5.118e-02 1.369e-01 2.100e+00 1.053e-01 5.184e-02 1.412e-01 2.300e+00 1.060e-01 5.223e-02 1.436e-01 2.500e+00 1.065e-01 5.251e-02 1.449e-01 2.700e+00 1.069e-01 5.274e-02 1.458e-01 2.900e+00 1.073e-01 5.293e-02 1.464e-01 3.100e+00 1.076e-01 5.309e-02 1.470e-01 3.300e+00 1.078e-01 5.324e-02 1.475e-01 3.500e+00 1.081e-01 5.344e-02 1.479e-01 3.700e+00 1.083e-01 6.705e-02 1.483e-01 3.900e+00 1.086e-01 2.529e+00 1.487e-01 4.100e+00 1.103e-01 1.438e+01 1.491e-01 4.300e+00 1.437e+00 2.638e+01 1.503e-01 Appendix A-16 DSP56364 Advance Information MOTOROLA IBIS Model 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [Pullup] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 1.800e+01 3.519e+01 5.241e+01 7.505e+01 1.007e+02 1.264e+02 1.522e+02 1.779e+02 2.036e+02 2.293e+02 2.550e+02 2.678e+02 3.839e+01 5.041e+01 6.419e+01 8.210e+01 1.000e+02 1.179e+02 1.359e+02 1.538e+02 1.717e+02 1.896e+02 2.075e+02 2.165e+02 1.810e-01 9.452e+00 2.664e+01 4.384e+01 6.224e+01 8.794e+01 1.136e+02 1.394e+02 1.651e+02 1.908e+02 2.165e+02 2.293e+02 I(typ) 2.677e+02 2.420e+02 2.163e+02 1.906e+02 1.649e+02 1.392e+02 1.135e+02 8.778e+01 6.208e+01 4.368e+01 2.649e+01 9.302e+00 3.838e-02 8.115e-03 5.634e-03 3.370e-03 1.118e-03 -1.09e-03 -3.12e-03 -4.96e-03 -6.60e-03 -8.04e-03 -9.26e-03 -1.03e-02 -9.03e-02 -9.49e-02 -9.84e-02 -1.01e-01 -1.03e-01 -1.05e-01 -1.06e-01 -1.07e-01 -1.08e-01 -1.09e-01 -1.10e-01 -1.11e-01 -1.11e-01 I(min) 1.896e+02 1.716e+02 1.537e+02 1.358e+02 1.179e+02 9.996e+01 8.205e+01 6.413e+01 5.035e+01 3.834e+01 2.633e+01 1.433e+01 2.477e+00 1.789e-02 3.503e-03 2.053e-03 6.789e-04 -6.56e-04 -1.86e-03 -2.93e-03 -3.87e-03 -4.66e-03 -5.30e-03 -4.75e-02 -5.02e-02 -5.21e-02 -5.34e-02 -5.45e-02 -5.54e-02 -5.62e-02 -5.68e-02 -5.74e-02 -5.79e-02 -5.84e-02 -5.89e-02 -6.49e-02 -1.23e+00 I(max) 2.677e+02 2.420e+02 2.163e+02 1.906e+02 1.649e+02 1.392e+02 1.135e+02 8.778e+01 6.208e+01 4.368e+01 2.649e+01 9.303e+00 4.183e-02 1.045e-02 7.064e-03 4.233e-03 1.410e-03 -1.38e-03 -3.99e-03 -6.39e-03 -8.59e-03 -1.06e-02 -1.23e-02 -1.41e-02 -1.23e-01 -1.31e-01 -1.38e-01 -1.43e-01 -1.47e-01 -1.50e-01 -1.52e-01 -1.54e-01 -1.56e-01 -1.57e-01 -1.59e-01 -1.60e-01 -1.61e-01 MOTOROLA DSP56364 Advance Information Appendix A-17 IBIS Model 4.100e+00 -1.14e-01 4.300e+00 -4.76e-01 4.500e+00 -2.73e+01 4.700e+00 -6.14e+01 4.900e+00 -9.54e+01 5.100e+00 -1.38e+02 5.300e+00 -1.89e+02 5.500e+00 -2.40e+02 5.700e+00 -2.91e+02 5.900e+00 -3.42e+02 6.100e+00 -3.93e+02 6.300e+00 -4.44e+02 6.500e+00 -4.95e+02 6.600e+00 -5.20e+02 | [GND_clamp] |voltage I(typ) | -3.30e+00 -5.20e+02 -3.10e+00 -4.69e+02 -2.90e+00 -4.18e+02 -2.70e+00 -3.67e+02 -2.50e+00 -3.16e+02 -2.30e+00 -2.65e+02 -2.10e+00 -2.14e+02 -1.90e+00 -1.63e+02 -1.70e+00 -1.13e+02 -1.50e+00 -7.83e+01 -1.30e+00 -4.42e+01 -1.10e+00 -1.02e+01 -9.00e-01 -1.03e-02 -7.00e-01 -3.74e-04 -5.00e-01 -1.72e-06 -3.00e-01 -1.67e-09 -1.00e-01 -2.03e-11 0.000e+00 -1.69e-11 | [POWER_clamp] |voltage I(typ) | -3.30e+00 2.677e+02 -3.10e+00 2.420e+02 -2.90e+00 2.163e+02 -2.70e+00 1.906e+02 -2.50e+00 1.649e+02 -2.30e+00 1.392e+02 -2.10e+00 1.135e+02 -1.90e+00 8.778e+01 -1.70e+00 6.208e+01 -1.50e+00 4.368e+01 -1.30e+00 2.649e+01 -1.10e+00 9.300e+00 -9.00e-01 2.962e-02 -2.16e+01 -4.52e+01 -6.89e+01 -9.25e+01 -1.17e+02 -1.52e+02 -1.88e+02 -2.23e+02 -2.59e+02 -2.94e+02 -3.30e+02 -3.65e+02 -4.01e+02 -4.18e+02 -1.62e-01 -1.64e-01 -1.73e-01 -7.82e+00 -4.19e+01 -7.59e+01 -1.11e+02 -1.61e+02 -2.12e+02 -2.63e+02 -3.14e+02 -3.65e+02 -4.16e+02 -4.41e+02 I(min) -3.65e+02 -3.30e+02 -2.94e+02 -2.59e+02 -2.23e+02 -1.88e+02 -1.52e+02 -1.17e+02 -9.25e+01 -6.88e+01 -4.51e+01 -2.15e+01 -1.17e+00 -5.73e-03 -5.06e-05 -4.65e-07 -4.80e-09 -1.61e-09 I(max) -5.18e+02 -4.67e+02 -4.16e+02 -3.65e+02 -3.14e+02 -2.63e+02 -2.11e+02 -1.60e+02 -1.10e+02 -7.58e+01 -4.17e+01 -7.66e+00 -9.27e-03 -1.14e-03 -1.28e-05 -1.10e-08 -2.71e-11 -1.89e-11 I(min) 1.896e+02 1.716e+02 1.537e+02 1.358e+02 1.179e+02 9.996e+01 8.205e+01 6.413e+01 5.035e+01 3.834e+01 2.633e+01 1.433e+01 2.475e+00 I(max) 2.677e+02 2.420e+02 2.163e+02 1.906e+02 1.649e+02 1.392e+02 1.135e+02 8.778e+01 6.208e+01 4.368e+01 2.649e+01 9.301e+00 3.075e-02 Appendix A-18 DSP56364 Advance Information MOTOROLA IBIS Model -7.00e-01 2.501e-04 1.354e-02 6.708e-04 -5.00e-01 2.066e-06 6.280e-05 1.204e-05 -3.00e-01 2.487e-09 5.128e-07 1.417e-08 -1.00e-01 5.672e-11 5.639e-09 6.832e-11 0.000e+00 5.334e-11 1.992e-09 5.783e-11 | [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) | | dV/dt_r 1.570/0.200 1.210/0.411 1.810/0.149 | | dV/dt_f 1.590/0.304 1.170/0.673 1.800/0.205 | [End]| [Model] ipbw_i Model_type Input Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [GND_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.17e+02 -3.10e+00 -4.69e+02 -3.29e+02 -4.66e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.15e+02 -2.70e+00 -3.67e+02 -2.58e+02 -3.64e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.13e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.62e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.11e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.24e+01 -1.10e+02 -1.50e+00 -7.82e+01 -6.87e+01 -7.57e+01 -1.30e+00 -4.42e+01 -4.51e+01 -4.16e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.64e+00 -9.00e-01 -7.17e-03 -1.16e+00 -4.87e-03 -7.00e-01 -1.14e-04 -4.39e-03 -3.03e-04 -5.00e-01 -4.86e-07 -2.55e-05 -2.73e-06 -3.00e-01 -5.19e-10 -1.91e-07 -2.57e-09 -1.00e-01 -1.91e-11 -2.47e-09 -2.19e-11 0.000e+00 -1.68e-11 -1.17e-09 -1.84e-11 | [POWER_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 2.667e+02 1.885e+02 2.667e+02 -3.10e+00 2.411e+02 1.707e+02 2.411e+02 MOTOROLA DSP56364 Advance Information Appendix A-19 IBIS Model -2.90e+00 2.155e+02 1.528e+02 2.155e+02 -2.70e+00 1.898e+02 1.350e+02 1.898e+02 -2.50e+00 1.642e+02 1.172e+02 1.642e+02 -2.30e+00 1.386e+02 9.935e+01 1.386e+02 -2.10e+00 1.130e+02 8.152e+01 1.130e+02 -1.90e+00 8.739e+01 6.369e+01 8.739e+01 -1.70e+00 6.178e+01 4.999e+01 6.178e+01 -1.50e+00 4.346e+01 3.806e+01 4.346e+01 -1.30e+00 2.634e+01 2.613e+01 2.634e+01 -1.10e+00 9.237e+00 1.421e+01 9.237e+00 -9.00e-01 2.454e-02 2.430e+00 2.488e-02 -7.00e-01 8.741e-05 1.104e-02 2.050e-04 -5.00e-01 6.316e-07 4.079e-05 2.961e-06 -3.00e-01 8.479e-10 2.484e-07 3.721e-09 -1.00e-01 4.420e-11 3.001e-09 4.943e-11 0.000e+00 4.215e-11 1.346e-09 4.543e-11 | [End]| [Model] ipbw_io Model_type I/O Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.17e+02 -3.10e+00 -4.69e+02 -3.29e+02 -4.66e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.15e+02 -2.70e+00 -3.67e+02 -2.58e+02 -3.64e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.13e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.62e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.11e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.24e+01 -1.10e+02 -1.50e+00 -7.82e+01 -6.87e+01 -7.57e+01 -1.30e+00 -4.42e+01 -4.51e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.66e+00 -9.00e-01 -3.69e-02 -1.17e+00 -3.79e-02 -7.00e-01 -2.52e-02 -1.67e-02 -2.81e-02 -5.00e-01 -1.83e-02 -9.77e-03 -2.04e-02 -3.00e-01 -1.11e-02 -5.89e-03 -1.24e-02 -1.00e-01 -3.77e-03 -1.98e-03 -4.20e-03 1.000e-01 3.729e-03 1.940e-03 4.177e-03 3.000e-01 1.076e-02 5.578e-03 1.216e-02 5.000e-01 1.723e-02 8.907e-03 1.965e-02 7.000e-01 2.311e-02 1.191e-02 2.663e-02 9.000e-01 2.836e-02 1.455e-02 3.305e-02 1.100e+00 3.292e-02 1.680e-02 3.887e-02 Appendix A-20 DSP56364 Advance Information MOTOROLA IBIS Model 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [Pullup] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 3.675e-02 3.979e-02 4.205e-02 4.347e-02 4.413e-02 4.445e-02 4.465e-02 4.479e-02 4.492e-02 4.502e-02 4.511e-02 4.519e-02 4.526e-02 4.536e-02 4.614e-02 1.344e+00 1.783e+01 3.495e+01 5.208e+01 7.463e+01 1.002e+02 1.259e+02 1.515e+02 1.771e+02 2.027e+02 2.283e+02 2.539e+02 2.667e+02 1.862e-02 1.997e-02 2.085e-02 2.136e-02 2.162e-02 2.176e-02 2.186e-02 2.194e-02 2.200e-02 2.206e-02 2.211e-02 2.219e-02 3.324e-02 2.452e+00 1.423e+01 2.615e+01 3.808e+01 5.001e+01 6.371e+01 8.154e+01 9.937e+01 1.172e+02 1.350e+02 1.529e+02 1.707e+02 1.885e+02 2.064e+02 2.153e+02 4.404e-02 4.850e-02 5.223e-02 5.518e-02 5.728e-02 5.843e-02 5.899e-02 5.931e-02 5.953e-02 5.971e-02 5.986e-02 5.999e-02 6.010e-02 6.021e-02 6.032e-02 6.065e-02 8.548e-02 9.298e+00 2.640e+01 4.352e+01 6.184e+01 8.745e+01 1.131e+02 1.387e+02 1.643e+02 1.899e+02 2.155e+02 2.283e+02 I(typ) 2.667e+02 2.411e+02 2.155e+02 1.898e+02 1.642e+02 1.386e+02 1.130e+02 8.739e+01 6.178e+01 4.346e+01 2.635e+01 9.243e+00 5.536e-02 2.847e-02 2.025e-02 1.208e-02 3.994e-03 -3.88e-03 -1.11e-02 -1.76e-02 -2.35e-02 I(min) 1.885e+02 1.707e+02 1.528e+02 1.350e+02 1.172e+02 9.935e+01 8.152e+01 6.369e+01 4.999e+01 3.806e+01 2.613e+01 1.421e+01 2.435e+00 2.689e-02 1.265e-02 7.503e-03 2.474e-03 -2.38e-03 -6.76e-03 -1.06e-02 -1.40e-02 I(max) 2.667e+02 2.411e+02 2.155e+02 1.898e+02 1.642e+02 1.386e+02 1.130e+02 8.739e+01 6.178e+01 4.346e+01 2.635e+01 9.245e+00 6.260e-02 3.437e-02 2.451e-02 1.467e-02 4.868e-03 -4.76e-03 -1.37e-02 -2.20e-02 -2.95e-02 MOTOROLA DSP56364 Advance Information Appendix A-21 IBIS Model 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [GND_clamp] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 0.000e+00 | -2.86e-02 -3.30e-02 -3.65e-02 -3.92e-02 -4.12e-02 -4.26e-02 -4.36e-02 -4.43e-02 -4.49e-02 -4.54e-02 -4.58e-02 -4.61e-02 -4.65e-02 -4.68e-02 -4.70e-02 -4.73e-02 -4.81e-02 -4.00e-01 -2.72e+01 -6.12e+01 -9.52e+01 -1.37e+02 -1.88e+02 -2.39e+02 -2.90e+02 -3.41e+02 -3.92e+02 -4.43e+02 -4.94e+02 -5.20e+02 -1.69e-02 -1.93e-02 -2.10e-02 -2.22e-02 -2.29e-02 -2.35e-02 -2.38e-02 -2.42e-02 -2.44e-02 -2.47e-02 -2.49e-02 -2.50e-02 -2.52e-02 -2.54e-02 -2.99e-02 -1.19e+00 -2.15e+01 -4.51e+01 -6.87e+01 -9.24e+01 -1.17e+02 -1.52e+02 -1.88e+02 -2.23e+02 -2.58e+02 -2.94e+02 -3.29e+02 -3.65e+02 -4.00e+02 -4.18e+02 -3.63e-02 -4.23e-02 -4.75e-02 -5.17e-02 -5.51e-02 -5.77e-02 -5.97e-02 -6.11e-02 -6.22e-02 -6.31e-02 -6.38e-02 -6.44e-02 -6.49e-02 -6.54e-02 -6.58e-02 -6.62e-02 -6.66e-02 -6.72e-02 -7.21e-02 -7.70e+00 -4.17e+01 -7.57e+01 -1.10e+02 -1.60e+02 -2.11e+02 -2.62e+02 -3.13e+02 -3.64e+02 -4.15e+02 -4.41e+02 I(typ) -5.20e+02 -4.69e+02 -4.18e+02 -3.67e+02 -3.16e+02 -2.65e+02 -2.14e+02 -1.63e+02 -1.13e+02 -7.82e+01 -4.42e+01 -1.02e+01 -7.17e-03 -1.14e-04 -4.86e-07 -5.19e-10 -1.91e-11 -1.68e-11 I(min) -3.65e+02 -3.29e+02 -2.94e+02 -2.58e+02 -2.23e+02 -1.88e+02 -1.52e+02 -1.17e+02 -9.24e+01 -6.87e+01 -4.51e+01 -2.15e+01 -1.16e+00 -4.39e-03 -2.55e-05 -1.91e-07 -2.47e-09 -1.17e-09 I(max) -5.17e+02 -4.66e+02 -4.15e+02 -3.64e+02 -3.13e+02 -2.62e+02 -2.11e+02 -1.60e+02 -1.10e+02 -7.57e+01 -4.16e+01 -7.64e+00 -4.87e-03 -3.03e-04 -2.73e-06 -2.57e-09 -2.19e-11 -1.84e-11 Appendix A-22 DSP56364 Advance Information MOTOROLA IBIS Model [POWER_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 2.667e+02 1.885e+02 2.667e+02 -3.10e+00 2.411e+02 1.707e+02 2.411e+02 -2.90e+00 2.155e+02 1.528e+02 2.155e+02 -2.70e+00 1.898e+02 1.350e+02 1.898e+02 -2.50e+00 1.642e+02 1.172e+02 1.642e+02 -2.30e+00 1.386e+02 9.935e+01 1.386e+02 -2.10e+00 1.130e+02 8.152e+01 1.130e+02 -1.90e+00 8.739e+01 6.369e+01 8.739e+01 -1.70e+00 6.178e+01 4.999e+01 6.178e+01 -1.50e+00 4.346e+01 3.806e+01 4.346e+01 -1.30e+00 2.634e+01 2.613e+01 2.634e+01 -1.10e+00 9.237e+00 1.421e+01 9.237e+00 -9.00e-01 2.454e-02 2.430e+00 2.488e-02 -7.00e-01 8.741e-05 1.104e-02 2.050e-04 -5.00e-01 6.316e-07 4.079e-05 2.961e-06 -3.00e-01 8.479e-10 2.484e-07 3.721e-09 -1.00e-01 4.420e-11 3.001e-09 4.943e-11 0.000e+00 4.215e-11 1.346e-09 4.543e-11 | [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) | | dV/dt_r 1.140/0.494 0.699/0.978 1.400/0.354 | | dV/dt_f 1.150/0.505 0.642/0.956 1.350/0.350 | [End]| [Model] iexlh_i Model_type Input Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [GND_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.21e+02 -3.66e+02 -5.18e+02 -3.10e+00 -4.70e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.19e+02 -2.95e+02 -4.16e+02 -2.70e+00 -3.68e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.17e+02 -2.24e+02 -3.14e+02 -2.30e+00 -2.66e+02 -1.89e+02 -2.63e+02 -2.10e+00 -2.15e+02 -1.53e+02 -2.12e+02 -1.90e+00 -1.64e+02 -1.18e+02 -1.61e+02 MOTOROLA DSP56364 Advance Information Appendix A-23 IBIS Model -1.70e+00 -1.14e+02 -1.50e+00 -7.93e+01 -1.30e+00 -4.53e+01 -1.10e+00 -1.13e+01 -9.00e-01 -7.94e-03 -7.00e-01 -1.62e-06 -5.00e-01 -3.45e-10 -3.00e-01 -1.29e-11 -1.00e-01 -1.10e-11 0.000e+00 -1.01e-11 | [POWER_clamp] |voltage I(typ) | -3.30e+00 2.653e+02 -3.10e+00 2.398e+02 -2.90e+00 2.143e+02 -2.70e+00 1.888e+02 -2.50e+00 1.633e+02 -2.30e+00 1.378e+02 -2.10e+00 1.123e+02 -1.90e+00 8.682e+01 -1.70e+00 6.133e+01 -1.50e+00 4.313e+01 -1.30e+00 2.614e+01 -1.10e+00 9.145e+00 -9.00e-01 1.797e-02 -7.00e-01 3.667e-06 -5.00e-01 7.730e-10 -3.00e-01 2.293e-11 -1.00e-01 2.096e-11 0.000e+00 2.004e-11 | [End] -9.34e+01 -6.98e+01 -4.62e+01 -2.26e+01 -1.87e+00 -5.11e-03 -1.40e-05 -3.90e-08 -8.67e-10 -7.13e-10 -1.11e+02 -7.68e+01 -4.28e+01 -8.78e+00 -3.77e-03 -7.69e-07 -1.72e-10 -1.38e-11 -1.19e-11 -1.10e-11 I(min) 1.870e+02 1.693e+02 1.516e+02 1.339e+02 1.162e+02 9.847e+01 8.076e+01 6.305e+01 4.947e+01 3.766e+01 2.585e+01 1.404e+01 2.364e+00 7.589e-03 2.072e-05 5.767e-08 1.163e-09 9.618e-10 I(max) 2.653e+02 2.398e+02 2.143e+02 1.888e+02 1.633e+02 1.378e+02 1.123e+02 8.682e+01 6.133e+01 4.313e+01 2.614e+01 9.145e+00 1.797e-02 3.667e-06 7.748e-10 2.476e-11 2.278e-11 2.186e-11 Appendix A-24 DSP56364 Advance Information MOTOROLA INDEX Numerics 5 V tolerance 1-1 2-5 wait states selection guide 2-33 write access 2-44 out of page and refresh timings A ac electrical characteristics address bus 1-1 ALU v Arithmetic Logic Unit v 11 wait states 2-39 15 wait states 2-41 4 wait states 2-33 8 wait states 2-36 Page mode B benchmark test algorithm A-1 Boundary Scan (JTAG Port) timing diagram read accesses 2-32 wait states selection guide 2-22 write accesses 2-31 2Page mode timings 65 bus external address 1-6 external data 1-6 bus control 1-1 1 wait state 2-23 2 wait states 2-25 3 wait states 2-27 4 wait states 2-29 refresh access 2-45 DSP56300 core features v DSP56362 features v specifications 2-1 C case outline drawing Clock 1-5 clock 1-1 external 2-6 operation 2-7 clocks internal 2-6 configuration v 3-6 E electrical design considerations 4-3 emory v Enhanced Serial Audio Interface 1-12 Enhanced Synchronous Audio Interface 1-1 ESAI 1-1, 1-12 receiver timing 2-61, 2-62 timings 2-57 transmitter timing 2-60 EXTAL jitter 4-5 external address bus 1-6 external bus control 1-6, 1-7 external clock operation 2-6 external data bus 1-6 external interrupt timing (negative edgetriggered) 2-15 external level-sensitive fast interrupt timing 2-14 external memory access (DMA Source) timing 2- D Data Arithmetic Logic Unit v data bus 1-1 DAX 1-1 dc electrical characteristics 2-3 design considerations electrical 4-3 PLL 4-5 power consumption 4-4 thermal 4-1 Digital Audio Transmitter 1-1 Direct Memory Access v DMA v DRAM out of page 16 MOTOROLA DSP56364 Advance Information Index - i Index External Memory Expansion Port 1-6, 2-17 F functional signal groups 1-1 G GPIO timing 2-63 Ground 1-4 PLL 1-4 ground 1-1 H HDI08 1-1 Host Interface 1-1 I internal clocks 2-6 interrupt and mode control 1-1, 1-8 interrupt control 1-8 interrupt timing 2-9 external level-sensitive fast 2-14 external negative edge-triggered 2-15 PCU v Peripheral modules vi Phase Lock Loop v, 2-8 PLL v, 1-1, 1-5, 2-8 Characteristics 2-8 performance issues 4-5 PLL design considerations 4-5 PLL performance issues 4-5 Port A 1-1, 1-6 Port B 1-1 Port C 1-1, 1-12 Power 1-2 power 1-1 power consumption benchmark test A-1 power consumption design considerations Program Control Unit v 4-4 R recovery from Stop state using IRQA 2-15, 2-16 RESET 1-8 Reset timing 2-9, 2-13 S Serial Audio Interface (ESAI) vi Serial Host Interface 1-1, 1-9 Serial Host Interface (SHI) vi SHI 1-1, 1-9 signal groupings 1-1 signals 1-1 SRAM read access 2-20 read and write accesses 2-17 write access 2-21 Stop state recovery from 2-15, 2-16 Stop timing 2-9 supply voltage 2-2 J Jitter 4-5 JTAG 1-16 JTAG Port timing 2-64, 2-65 JTAG/OnCE port 1-1 M maximum ratings 2-1, 2-2 mechanical drawings 3-6 Memory v Memory Configuration v Mfax system 3-6 mode control 1-8 Mode select timing 2-9 T Test Access Port timing diagram 2-65 Test Clock (TCLK) input timing diagram 2-64 thermal characteristics 2-2 thermal design considerations 4-1 Timer 1-1 Timing Enhanced Serial Audio Interface (ESAI) O OnCE module 1-16 operating mode select timing ordering drawings 3-6 ordering information 5-1 2-15 2- P package TQFP description 59 3-1, 3-3 General Purpose I/O (GPIO) Timing OnCETM (On Chip Emulator) Timing 2-57 2-57 Index - ii DSP56364 Advance Information MOTOROLA Index Serial Host Interface (SHI) SPI Protocol Timing 2-46 Serial Host Interface (SHI) Timing 2-46 timing interrupt 2-9 mode select 2-9 Reset 2-9 Stop 2-9 TQFP pin list by number 3-3 pin-out drawing (top) 3-1 TQFP package drawing 3-6 MOTOROLA DSP56364 Advance Information Index - iii DSP56364 iv DSP56364 Advance Information MOTOROLA Symphony and OnCE are registered trademarks of Motorola, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such are claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/Europe/Locations Not Listed: Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 1 (800) 441-2447 1 (303) 675-2140 Asia/Pacific: Motorola Semiconductors H.K. Ltd. 8B Tai Ping Industrial Park 51 Ting Kok Road Tai Po, N.T., Hong Kong 852-26629298 Technical Resource Center: 1 (800) 521-6274 DSP Helpline dsphelp@dsp.sps.mot.com Japan: Nippon Motorola Ltd. SPD, Strategic Planning Office 4-32-1, Nishi- Gotanda Shinagawa-ku, Tokyo 141, Japan 81-3-5487-8488 Internet: http://dspaudio.motorola.com |
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